Anna University Coimbatore 2010 B.E Electronics
ANNA UNIVERSITY COIMBATORE B.E. I B.TECH. DEGREE EXAMINATIONS : MAY / JUNE 2010 REGULATIONS : 2007 SIXTH SEMESTER : ELECTRONICS & COMMUNICATION ENGINEERING 070290070 - VLSI DESIGN TIME : 3 Hours Max.Marks : 100
PART - A
ANSWER ALL QUESTIONS
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1. |
Define Layout Editor |
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2. |
What is Reactive Ion Etching (RIE)? |
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3. |
Define Yield |
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4. |
Draw the PFET masking sequence |
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5. |
List the classifications of design rules |
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6. |
Give the equation for PFET resistance Rp |
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7. |
Write the level 1 SPICE MOSFET parameters |
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, 8. |
Define Body bias |
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9. |
Draw the circuit diagram of Tristate Inverter |
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10. |
Write the sum and carryout equation of full-adder |
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11. |
Draw the layout of a 2-Input NOR gate by using CMOS logic |
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12. |
Define drift current |
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13. |
Define threshold and give the threshold equation for nFET structure |
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14. |
What is ring Oscillator? |
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15. |
Why charge leakage occurs in CMOS circuits? |
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16. |
What do you mean by domino logic? |
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17. |
Write the syntax for FOR/GENERATE Statement |
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18. |
Compare Signal and Variable |
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19. |
List the syntax of WAIT UNTIL statement with example |
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20. |
Define sensitivity list for Process statement. |
PART -B
ANSWER ANY FIVE QUESTIONS
21. a. Give the step-by step evolution of the chip from bare Silicon wafer to the (8)
finished product based on CMOS fabrication
b. Discuss in brief the operation of basic NMOS enhancement transistor (4)
22. a. Write the SCMOS design rules for N-well,P-diffusion,Poly1,Contacts, Metal 1 (8)
and Vial layers
b. Define Photolithography. Give the sequence used to create the pattern (4)
23. a. Discuss in detail about the electrical & transient characteristics of CMOS <8)
Inverter
b. What do you mean by latch-up in CMOS circuits and give certain remedies (4) for the latch-up problem
24. a. Realize the following function using complex logic gates (8)
i) g= a.b+c.d ii)h=(a+b).(c+d)
b. Draw the Euler graph for the function F=(a+b).c (4)
25. a. Explain the function of static RAM cell with its SPICE Simulation (8) b. With neat diagram explain the function of Master-Slave D-type flip-flop (4)
26. a. Write a VHDL code for a 4-to-1 multiplexer by using CASE Statement. (6) b. Write a VHDL code for a 8x3 encoder by using WHEN/ELSE Statement (6)
27. a. Write a VHDL program for a Mealy state machine in any one modeling (8) b. Compare Concurrent and Sequential Statement (4)
28. a. Explain in detail about the Transmission gates and pass logic (8) b. Briefly explain about series connected FETs. (4)
*****THE end*****
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Attachment: |
| Earning: Approval pending. |
