Osmania University (OU) 2006-1st Sem B.E Electronics & Tele-Communication Engineering 3/4 (E.C.E)(ESTER)SUPPLEMENTARY ,IL, Digital integrated circuits and applications - Question Paper
B.E 3/4 (E.C.E)(I-SEMESTER)SUPPLEMENTARY EXAMINATION,APRIL,2006
Digital integrated circuits and applications
> * Code No.: 10294
FACULTY OF ENGINEERING B.E. ra/IV Year (ECE) I Semester (Supplementary) Examination, May 2006
; - ' DIGITAL imGRAlD CIRCUlTS AND APPLICATIONS Time : 3 Hours] " {Max. Marks : 75
Answer all questions of Part A.
Answer five questions from Part B.
Part A - (Marks : 25)
''' i . 4 ; ; '* ':t : "
1. Show the circuit diagrams of AND, OR, NOT in DTLfamily. 3
2. Write threeadvaritagesof CMOS logic, 3
3. Write the description of the following JCs : 3
(a) 74AUS&) (b) 74HSOO (c) 74 LS32
4. Distinguish between an encoder and decoder. 2
5. What are the advantages of synchronous counters? 3
6. Show the diagram of a 3-bit binary up counter. 2
7. Distinguish between ROM, static RAM and dynamic RAM. 3
8. Define memory word and memory cell. 2
9. Write the advantages of PLDs.' 2
10. What is the difference between FPGAs and gate arrays? 2
Part B - (Marks : 5 x 10 = 50)
11. (a) Explain IC interfacing techniques for CMOS and TTL families. 5
(b) Draw the circuit diagram of a 2-input ECL NOR/OR gate and explain the operation with the truth tables. 5
12. (a) Design a gray to BCD converter using (i) Dual 4:1 multiplexor IC and same
gates. 5
(b) Design a 4-bit magnitude comparator and show the logic diagram. 5
13. (a) What is the race around problem in J-K flip flop? Explain how it is eliminated in
J-K MS flip flop. Show the truth tables. 5
(b) Explain the operation of a 4-bit universal shift register with circuit diagram. How do you realize a Johnson counter using shift register? 5
14. (a) Realize a 32K byte RAM system using 16K x 4 memory chips. Give the address
map. ...... .. . .. j* 5
(b) Draw the structure of a DRAM cell and, fplain its* function. Also explain DRAM refreshing and address multiplexing. 5
15. (a) Compare PAL and PLA with the help of block schematics and explain the
respectives advantages. i* 5
(b) Discuss full custom and semi custom ASKs and their architectures. 5
16. (a) Design a Mod-6 asynchronous counter using T-FFS with clear inputs. Explain
its function using timing diagram. 5
(b) Draw the circuit diagram of an R-S latch and explain. Discuss how a debounce circuit eliminates the problems of this circuit. 5
17. (a) Design and explain with waveforms the operation of a divided by-12 ripple
counter. What are the advantages of ripple counters? 5
(b) Explain parallel, serial and fast-serial binary adders with circuit diagrams. 5
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| Earning: Approval pending. |
