Guru Gobind Singh Indraprastha Vishwavidyalaya 2009-4th Sem B.E Electronics & Communication Engineering DIGITAL CIRCUIT & SYSTEM-1 - - Question Paper
END TERM exam
FOURTH SEMESTER [B.TECH]-MAY-JUNE 2009
DIGITAL CIRCUIT & SYSTEM-1
(Please write your Exam Rotl No.) Exam Roll No. ... {4--
Fourth SEMESTER [B.Tech.}- Mav- Juke 2009_________
Paper Code: ETBC-206 Subject: Digital Circuits & System-I
Paper ID: 28206 (Batch: 2004-2007}
Time : 3 Hours__________________________Maximum Marks :75
Note: Attempt any Jive questions.
Q. 1 L&\ Whih of the following are incorrect representation and why?
(ir 1010011 |X,I (1*K 0208OC, 10102011 binary
- GGOAhexsidccimal (v) 120Adccimal
Divide a number 0111 1011 111 1001 by divisor 01 U.l 111J-U0 0011\ (jSp' [o/] Show by an example that we can subtract both positive and negative numbers by two's complement arithmetic.
Q.2 Simplify A.C + A.(C+B) *- C.(C+B) using Boolean rules and draw the simplest
possible logic circuit. \> my
Convert POS (A+B+C.D) expression into standard four variables POS format / four variables. 2-14)
Simplify after first converting (a.B.c)+(a.0.d) to standard POS form and .
then using K map to make a circuit with NOR gates only. ij <7 r
Q.3 Design and implement the function F B 11 M (1, 7, 9, 15) using 4:1 MUX. (8)
(bf Give logic design and implement the Boolean functions Fi = S m (3, 7, 9, 10)
< and F-2 - 2 m(2, 7, 12, 15J using decoder. (7)
Q.4 [ay . Explain why gated SR latch is called a transparent latch? Show the timing
< diagram for gated SR later with clock input (active level 1). (7) ,
(b) j Consider a JK flip flop i.e. a JK flip flop with an inverter between external 1 S input K and internal input K. (i) Obtain the flip flop characteristics table (ii) obtain the characteristic equation (iii) show that tying the two external inputs together forms a U flip flop. (8)
Q.5 (a) Kxplain the working of Modulo-10 (decode) countcr and implement the logic
circuit using JK ff. (8)
(b) Design a 4-bit buffer register with parallel output after storing. |7)
Q.6 (a) An astable multivibrator uses timer 555. It is required that duty cycle is 0.58 and frequency is 10 KHz. If capacitor used is of .001 p.F then find the value of resistances to obtain desired duty cycle. Can we obtain duty cycle of 0.5? (7)
(b) If digital output of a 12-bit ADC is 1000 0111 1111 then find the resolution and the input at that instance when Vper/2 = 0.75V. (4)
(c) Give circuit diagram and explain working of successive approximation ADC. (4)
Q.7 jalf' Kxplain following terms w.r.t. logic families (i) speed (ii) 1 2,
propagation delay (iii) operating frequency (iv) power dissipated per gate (v) ( fan out (vi) fan in (vii) noise immunity (viii) Von, VJH, Vov, Vjl,. (8)
(b) Compare and contrast MOS and Bipolar logic families. Also give applications. (7)
Q.8 (a) A dynamic RAM needs refresh every few milli seconds and a static RAM need
not. Why? (7)
(b) Differentiate between PAl, & PLA. What is the advantage of tristate outputs and registered outputs provision in PAL? (8j
Q.9 Write short notes (any three) (15)
(a) Content addressable memory n/
Binary-weighted DAC
(c) Nyquist sampling theorem
(d) Drivers for display devices
(e) Dont care conditions
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