Cochin University of Science and Techology (CUST) 2006 B.Tech Electronics and Communications Engineering Title: VLSI Design - Question Paper

BTS(C) - VII - 06 - 046 (C)

B.Tech. Degree VII Semester Examination, November 2006

EC 703 VLSI DESIGN

(2002 Admissions onwards )

Maximum Marks: 100

Draw and explain the process of n-well CMOS fabrication.    (8)

Discuss the flow diagram of n-well technology.    (6) Compare between monolithic and hybrid ICs Mid also mention about its

application areas?    (6)

OR

Explain why GaAs is preferred than Si in microwave monolithic ICs.    (5)

Compare the material properties of GaAs and Si.    (5) Discuss about the high current and high energy ion implantation equipment and

explain how it varies from a typical ion implanter with relevant diagram.    (10)

Derive an expression for drain current for long channel MOSFET and explain the

various modes of operation under different voltages.    (10)

Discuss about various second order effects in MOSFETS.    (10)

OR

Derive an expression for puil up to pull down ratio for an NMOS inverter driven by another NMOS inverter.    (10)

A PMOS structure has a substrate doping of N_d=10¹⁶cm³ and a gate doping of Nd=10²⁰cm"³. The oxide charge density is Q_0K=4 x 10ⁱ⁰ q=6.4nC/cm² and thickness is to_X=1000 angstroms.

   Calculate the threshold voltage with zero substrate bias

   Calculate the body coefficient y    (10)

Discuss the need of design rules? What is the difference between X rules and micron rules. Draw the circuit diagram; stick diagram and layout of a two input CMOS NAND gate?

OR

a)    Discuss the need of super buffers and explain the working of inverting and non-inverting super buffers.

b)    Explain the concept of sheet resistance and MOS device capacitance with relevant Equations.

a)    Discuss the various implementation strategies of digital ICs.

b)    Explain the working of clocked CMOS (C MOS) logic with diagram.

OR

a)    Explain the working of a two input XNOR gage using pass transistors.

b)    Implement the function Z=(A.B)+(C.D) using CMOS logic and draw its stick diagram.

a)    What is clock skew and discuss the effect of positive and negative clock skew on clock period with relevant diagrams and equations?

b)    Explain the concept and implementtion of synchronizers.

OR

Write short notes on:

(i)    Synchronous versus asynchronous

(ii)    Self timed circuit design

(iii)    Clock distribution techniques

(20)

Attachment: cochin-university-of-science-and-techology--cust--2006-b-tech-electronics-and-communications-engineering-37147-1.pdf

Earning:   Approval pending.