Punjab University 2008 B.E Information Technology UNIVERSITY S - Question Paper

B.E IT third SEMESTER
DIGITAL ELECTRONICS

SUb* Code i 2961

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2118

B* s* (I* T) 3rd semester IT-315 Digital Electronics Time Allowed:3 Hours    Max*Marks; 100

Note* Attempt any five questions, selecting atleast two questions from each Part a and Part-B*

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I (a) 3xpress the following nos, in decimal:

(10110_#01G1>2 , <l6.Sj_i6 and (26*24)8*

The solution to the quadratic aquation y?~*llx.+22Q is x=3 and 3c6* Wlmt is the base of the numbers?

(c)    Convert the hedecimal no* 68BE to binary and then binary, convert it to actual#

(d)    Represent decimal no#6027 in (i)B<2> (ii)Excess ~3 code (iii) 2421 code*    (6,4,4,6)

(a)    Define positive and Negative logic* Represent universal gates with help of it How is De-Morgan* s theorem related to it? Also convert NAND to SX-OR ' gate using minimum no* of gates*

(b)    Inclement F(a,B,C,D) (1,3,4,11,12,13,14) using a 8sl MUX*

(c)    Design a BCD-to-7*segment decoder*    (6,6,8)

III    (a) using 10*3 complement, subtract 3250-72532*

(b) siirlify using Boolean algebra only:~

K=X?2H-5d?Z+W X+WCC+WX*

Also obtain truth table and draw logic diagram using sin$>lified egression*    (8,12)

IV    (a) Design a counter with the following repeated binary

sequence: 0,1,2,3,4,5*6* Use THK flipflops*

(b) What is the difference between serial & parallel transfer? Explain how to convert serial data ,to parallel and parallel data to serial, what type of register is needed?    (10,10)

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V (a) Design a combinational circuit using a RDM* The

tkt* accepta a 3-bit number and generates an output binary no* equal to the square of the irput number

(b) Draw and explain the circuit diagram for a 16-bit

RDM array using diode matrix coufig**    (10* 10)

vi The following are the specifications for the schottky TTL 74500 quadrap 1 <3 two~ir>ut NAJSD pates* CHlcUlate the fan ,-oufc, power dissipationpropagation delay and noise margin of the schottky NAND gate*

Parameter	Name	v&lue
vcc	Supply voltage	5V
JCCH	High-level supply current	10mA
JCCL	Lowlvel supply current	20mA
VeK	High-level o/p voltage (min)	2* 7V
V0L	Low-level o/p voltage (max)	0,5V
Yin	High-level l/P voltage (min)	2V
vil	I/P voltage (max)	0*8V
	High-level o/p current (max)
, i.' %QL	Low-level o/p current (max)	20mA
	High-level I/P Current (max)	0* 05mA
lj:1L	Low-level I/P current (max)	2ha
t'P-LH __L	Low-to-high delay	3ns
"T	High-to-iow delay	3ns
<b) E3q>lain with the aid of a circuit diagram.		the operation

of a standard TTL 3-input NAND gate* What is the function of diode in the path of otempole output stage?    (8,12)

VII    (a) Host DAC^#s are of either the Binary weighted resistor,

or the R-2R type* What are the disadvantages of the former and when might it be employed?

(b) What are the various processes, followed in an ordered sequence for converting an analog signal to a digital form? How can quantization error be reduced? (10,10)

VIII    Write short notes on the following* -

(a)    Tristate Logic

(b)    Slash type ADC

CCj CM0s Inverter*

Cd) Reading operate

Attachment: punjab-university-2008-b-e-information-technology-31452-1.pdf

Earning:   Approval pending.