Thapar University 2010 B.E Computer science information technology (CSIT) Computer System Architecture - Question Paper

Course Code: CS004

Course Name: Computer System Architecture Instructor: Prateek Bhatia, Karun Verma, Navjot Kaur

Note: All the Questions are compulsory and attempt in order. Use of Calculator is not allowed. Draw neat and clean diagrams w^rherever required.

1.    a) Design a sequential circuit with two T flip-flops A and B and tw^fo 3

inputs E and x. When E=0, the circuit remains in the same state regardless of the value of x. When E=I and x=l the sequence is

00,11,10,01,00 and repeat. When E=1 and x=0, the sequence is

00,01,10,11,00 and repeat,

b) A computer System has 24 address lines, for a total memory 3 addressability of 2²⁴=16 MB. However, the system needs to be provided with only 2 MB of physical memory, by making use of two memory devices of 1 MB each. The 2MB of memory provided are to occupy the lowest addresses in the total addressable memory of the system. Outline using a circuit diagram how you would decode and make use of the 24 system address lines to achieve this design objective.

2.    a) Using 8-bit twos complement integers, perform the following 2

4

3

i)    Add a register to the bus system CTR (count register) to be selected with S2SiSo=000

ii)    Replace the ISZ instruction with an instruction that loads a number into CTR

LDC address CTKrMladdress]

iii)    Add a register reference instruction ICS: increment CTR and skip next instruction if Zero. Discuss the advantage of this change as compared to ISZ.

b) Design an arithmetic circuit w'ith one selection variable S and two 3 n-bit data inputs A and B. The circuit generates the following four arithmetic operations in conjunction with input carry C_in. Draw the logic diagram for the first two stages.

S C_in=0

Fetch RT,: AR 4- PC RTt: IR 4- M[AR], PC 4- PC + 1 Decode RT,: DO,.... D7 4- Decode IR(12 - 14), AR <- IR(0 - 11), 1 <- IR(15) Indirect D/IT,: AR 4- M[AR] Interrupt T0T,T2'(IEN)(FGI FGO): R4-1 RT#: AR 4- 0, TR 4- PC RT,: M[AR]4-TR, PC 4-0 RT,: PC 4- PC * 1, IEN 4- 0, R 4- 0, SC 4- 0 Memory-Reference AND D0T<: DR4-M[AR] D0T,: AC f- AC a DR, SC 4 0 ADD D,T4: DR 4- M[AR] D,T#: AC 4~ AC + DR, E 4- Ceol, SC 4-0 LDA DaT4: DR4-M[AR] D.T.: AC 4- DR, SC 4- 0 STA D,T<: M[AR]<- AC, $0 4-0 BUN D J,: PC+-AR, SC 4-0 BSA D,T4: MIAR]4-PC,AR4-AR*1 DsTb: PC 4- AR, SC 4-0 ISZ DT4: DR 4- M[AR] DT5: DR 4-DR 4-1 D.T.: M[AR] 4- DR, H(DRsO) then (PC 4- PC 4 1),

SC 4- 0

Design Hardware on Common Bus System for Memory (Read,Write), AR(Increment, Load), PC(Load, Increment)

5. a) What is the importance of overflow in Arithmetic Shift operation? 2 How it is detected?

b)    Design a common bus system for 16 registers 4-bit each using 2 three state bus buffers.

i

c)    Simplify the Boolean function F together with the dont care 2 conditions d in (1) sum of product from and (2) product of sum form

F(w₉x_ty_tz)-'L(0₉l,2_tl7,8_tlQ) d(w_tx,y,z)='L(5,6,11,15)

Attachment: thapar-university-2010-b-e-computer-science-information-technology--csit--25976-1.pdf

Earning:   Approval pending.