Anna University Chennai 2011-6th Sem B.E Electronics & Communication Engineering ./B.Tech , IL/ , ester, Electronics and Communication Engineering, EC 2354- VLSI DESIGN, REGULATION 2008 - Question

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2011,
Sixth Semester,
Electronics and Communication Engineering,
EC 2354- VLSI DESIGN,
REGULATION 2008

Reg. No.

Question Paper Code : 11300

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2011 Sixth Semester Electronics and Communication Engineering EC 2354 VLSI DESIGN (Regulation 2008)

Answer ALL questions PART A (10 x 2 = 20 marks)

1.    Draw the energy band diagrams of the components that make up the MOS system.

2.    What is body effect coefficient?

3.    What is the influence of voltage scaling on power and delay?

4.    Express 7'_;w and T_PLH in terms of C_w .

5.    Draw the circuit diagram of a CMOS bistable element and its time domain behavior.

6.    Write a note on CMOS transmission gate logic.

7.    Write a note on partition and MUX technique.

8.    List the design guidelines for I_nDQ testing.

9. What is transport delay model?

10. What is subprogram overloading?

PART B (5 x 16 = 80 marks)

11. (a) (i) Explain in detail with a neat diagram the fabrication process of the

nMOS transistor.    (8)

(ii) Discuss in detail with a neat layout, the design rules for a CMOS inverter.    (8)

Or

(b) (i) Discuss in detail with necessary equations the operation of MOSFET and its current- voltage characteristics.    (11)

(ii) Explain briefly CMOS process enhancements.    (5)

12. (a) Explain in detail about

(i)    Channel length modulation.

(ii)    Constant field scaling.

(iii)    Constant voltage scaling.

Or *

(b) With necessary equations, explain in detail about:

(i)    Short current effect.

(ii)    Narrow channel effect.

13. (a) (i) For a resistive load inverter circuit with

V_DD =5 V,K' = 20 mA/V², V_ro =0.8 V,R_L =200 kQ., and = 2.

Calculate the critical voltages on the voltage transfer characteristics and find the noise margins of the circuit.

(ii) Explain the detail about pseudo- nMOS gates with neat circuit diagram.    (10)

Or

(b) (i) Design a transistor level schematic of the one bit full adder circuit and explain.    (6)

(ii) Discuss in detail the characteristics of CMOS transmission gate.(10)

14.    (a) Explain in detail the sequence of Scan-Based techniques.    (16)

Or

(b) With the essential circuit modules, explain in detail the BIST technique.

(16)

15.    (a) (i) How is component instantiations bound? Explain it using a one

Or

(iii)    Write VHDL coding for a decoder circuit:

(1)    Dataflow model.

(2)    Behavioral model.    (3)

3    11300

Attachment: anna-university-chennai-2011-b-e-electronics--amp--communication-engineering-12619-1.pdf

Earning:   Approval pending.