Bengal Engineering and Science University 2007 B.E Computer Science and Engineering Electronic design automation - Question Paper

The ques. paper is with the attachment.

4^th Semester Final Examination 2007 Subject :Electronic Design Automation (CS404)

Time: 2 hours    J,    FM: 35

I

(i)    Answer two from each hSf

(ii)    Three marks reserve for neatness

Group-A

1(a) What are the basic design methodology in verilog HDL? Discuss with example.

(b) A full subtractor has three 1 bit inputs P.Q.R (previous borrow). Write the full verilog description for the full subtractor module, including I/O ports. Instantiate the subtractor inside a stimulus block and test all eight possible combinations of P,

Q and R.

2(a) What is procedural continuous assignment? Discuss about the different types of procedural continuous assignment.

(b) Using assign and deassign statements, design a positive edge triggered D-FF with asynchronous clear (q=0) and preset (q=l).

3(a) Mow to override the parameter values in a module?

(b) Build the fulladd4 module with defparam statements to change instance parameter values.

Group-B

4(a) What are the differences between function and procedure in VHDL?

(b) What is the use of package declaration and package body?

( c) How configuration declaration differs from configuration specification?

5(a) What is the basic difference between data How style of modeling and 2+2 behavioral style of modeling. What is the function of the process statement in a behavioral style of modeling?

(b) Discuss with example, the use of next, exit, wait and null statement in VHDL 4 code.

6" Write a VHDL code for 3 bit bidirectional shift register.    8

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Attachment: bengal-engineering-and-science-university-2007-b-e-computer-science-and-engineering-1054-1.pdf

Earning:   Approval pending.