West Bengal Institute of Technology (WBIT) 2009-6th Sem B.Tech Electronics and Communications Engineering Electronics & Comm ( - ) VLSI Circuits & Systems - Question Paper
CS/B.Tech (BCE)/SEM-6/EC-604/09 3
ENGINEERING & MANAGEMENT EXAMINATIONS, JUNE - 2009
VLSI CIRCUITS & SYSTEMS
SEMESTER - 6
Time : 3 Hours
[ Full Marks : 70
GROUP - A ( Multiple Choice Type Questions)
1. Choose the correct alternatives for any ten of the following
10 x 1 = 10
i) What is another name of D. Gzaski chart ?
a) Y Chart c) Z Chart
b) Smith Chart
d) Log Chart.
ii) Channel-less Gate array is a sub-type of
a) FPGA c) ASIC
b) PLD
d) None of these.
iii) Minimum number of transistors required to implement F = ABC + DE + F is
a) 5 c) 7
b)
d) none of these.
iv) The output of physical design is
a) Circuit diagram
c) Lay-out
b) Mask d) RTL.
v) DRAM is widely used because
a) refreshing operation is hot needed
b) of low cost and high density
c) of low power consumption
d) of high speed.
vi) Data refresh operation is needed in
a) DRAM b) Flash
c) SRAM d) FRAM. |
vii) For a symmetrical CMOS inverter the relation between aspect ratio of NMOS and . PMOS is
a) ( W/L) p = ( W/L ) n b) ( W/L) p = 2-5 ( W/L) n
c) ( W/L) n = 2-5 ( W/L) p d) ( W/L) n = 5 ( W/L) p .
viii) Frequency compensation of Op-Amp using MOS technology is done by
a) decreasing the number of stages
b) minimizing the number of poles in single path
c) achieving low voltage gain
d) all of these.
ix) A BJP is considered as Open Switch ( or OFF ) when
a) both junctions are forward biased
b) EBJ is forward and CBJ is reverse
c) both junctions are reverse biased
d) EBJ is reverse and CBJ is forward.
18844 ( 1S/06T
3 Hierarchical decomposition of a large system in VLSI design is called
b) regularity d) none of these.
a) modularity c) locality
xi) Which of the following is not a part of FPGA ?
b) I/O Block
a) CLB
c) Vertical routing channel
d) FSM.
xii) The quantisation noise of a DAC having N number of bits is
N- 1
a) directly proportional to 2 N
b) directly proportional to 2
c) inversely proportional to 2 N
d) inversely proportional to 2 N ~1
GROUP - B ( Short Answer Type Questions)
Answer any three of the following. 3 x 5 = 15
What is MOSFET scaling ? What is the need of scaling ? Compare various types of scaling. 1 +2 + 2
Explain the following phenomenon in an MOS structure : 3 + 2
a) Channel length modulation
b) Pinch-off.
a) What do you mean by VHDL ? Why is it required in VLSI circuit simulation ?
I + 1
3
b) Derive saturation current in an n-MOS transistor.
5. a) What Is current mirror ?
b) With circuit diagram explain the operation of an MOS current mirror. 1+4
6. Draw the layout and schematic diagram of a 2-input static CMOS NO ft Gate and identify the corresponding components in the two drawings. 1 + 1+3
GROUP -C ( Long Answer Type Questions)
Answer any three of the following. 3 x 15 = 45
7 a) What is Y cycle in VLSI ? Explain VLSI design cycle in detail. 2 + 6
b) What do you mean by standard cell design ? How does it differ from gate arrray design ? 2 + 3
c) What is top-down and bottom-up design in VLSI ? 2
8. a) Design a static CMOS circuit to implement the Boolean function :
F = AB + AB'C + A1 C1. 7
b) Draw the CMOS half adder circuit and explain its operation. 5
c) Explain why NMOS is preferred for pull-down network and PMOS is preferred for pull-up network. 3
9. a) Design the following circuit using PAL, PLA and ROM :
Y 1 = AB + A1 C + ABC1, Y2 = AB1 C, Y3 = BC + ABC1 6
b) Design a master-slave D flip-flop. Describe its operation. 3
c) Describe the read and write operation of a six transistor SRAM cell. 6
10. a) Explain lambda ( X) design rules In VLSI. 4
b) Compare the advantage of lambda design rule over micron rule. 3
c) What is CMOS twin tub process ? Explain. 3
d) Find out an expression for dynamic power dissipation in CMOS. 3
e) What are the properties of VLSI interconnects ? 2
11. a) Discuss the merits and demerits of Flash ADC. Find resolution for a DAC if the
output voltage is desired to change in lmV increments while using a reference voltage of 5V ? 2 + 3
b) How can a MOS device be used as a voltage reference ? 5
c) What do you mean by hierarchy, regularity, modularity & locality of any ASIC design. 5
END
6844 ( 15/06)
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| Earning: Approval pending. |
