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Rajasthan Technical University 2011-2nd Sem B.Tech Computer Science and Engineering I (Main & Back),- , Digital Electronics (3CS5) - Question Paper

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3E2075

B.Tech. Illrd Semester (Main/Back) Scheme Examination, Feb. - 2011 Computer Engineering & Information Technology 3IT5 & 3CS5 Digital Electronics

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Time : 3 Hours    Maximum Marks : 80

Min. Passing Marks : 24

Instructions to Candidates:

Attempt overall five questions, selecting one question from each unit. Schematic diagrams must be shown wherever necessary. Any data you feel missing may suitably be assumed and stated clearly.

Unit-I

1. a) Convert the decimal number 250.5 to base 3, base 4 and base 7.    (6)

b)    Find the 10s complement of (935)n.    (2)

c)    Find the equivalent Gray Code for (478)10.    (2)

d)    Obtain the weighted binary code for base -10 digits using weights of5421 .(2)

e)    Find the complement of the following boolean functions by finding dual of them:

0 F(A,BX) = (A + B' + C)(A + B')(B + C)(A + B + C).

ii) F( vv, y> z) = yz + wxy + wxz' + w'x'z .    (4)

OR

a)    Represent the decimal number 2047 as

i)    Radix - 2 number

ii)    BCD code

iii)    8, 4, -2, -! code

iv)    Excess -3 code    (4)

b)    Represent (-17)t0 in

i)    Sign Magnitude form

ii)    1 *s complement representation    (2)

c)    Find the radix V for the following equations to be valid :

0 V7l = 8

ii) f = 15    (4)

d) Perform the following :

i)    (72532)|0-(3250)|0 10s complement subtraction.

ii)    (28)10 + (95)10 BCD Addition.

iii)    (74)8 - (35)8 7s Complement subtraction.    (6)

Unit - II

2.    a) Explain the functioning of following gates using appropriate circuit - diagram:

i)    CMOS NAND Gate

ii)    CMOS NOR Gate    (6)

b)    Tabulate the comparison between different logic families on the basis of their typical characteristics.    (6)

c)    Write a short note on :

Propagation Delay in Digital logic gates.    (4)

OR

a)    Explain the functioning of following gates using appropriate circuit - diagram:

i)    TTL Gate with open - collector.

ii)    TTL Gate with Totem - pole output.    (8)

b)    Explain the function performed by the wired - OR gate with its circuit diagram.

(4)

c)    Explain the following:

i)    Power Dissipation

ii)    Noise Margin    (4)

Unit-III

3.    a) Simplify the boolean function by using quine - McCluskey method :

11,15) + */(0,2, 5).    (8)

b)    Simplify the following boolean function using K-map and give simplified expression in SOP form :

F (A, B, C,D) = II (0, 1, 2, 3, 4,10J1)    (4)

c)    Minimize the following expressions by using the basic laws of boolean algebra:

i)    Y = AB + AC + ABC(AB + C)

ii)    Y = ABC + BCD + AC + ABCD    (4) 3E2075 (2) '




F - Z(w' + y)

is a simplified version of the expression F = (W + y)(jc' + z)(w' + z)

Find the dont care conditions, if any.

Simplify the following boolean function, using the dont care conditions d, with K-map and realize the simplified expression with NOR gates only.(8)

b)

c)

4. a)

b)

c)

a)

b) c)


F = A'B'D'+A'CD + A'BC d = A'BCD + A CD + AB'D

Express the function

F = A+~BC    (2)

i)    in canonical SOP form

ii)    in canonical POS form.    .

Unit-IV

Design a 4-bit parallel ADDER/SUBTRACTOR circuit with ADD/SUB control line.    (6)

Design and implement a Full-Subtractor circuit using 3-to-8 decoder and external gates.    (4)

Design and implement a combinational circuit for addition of two one-digit BCD numbers.    (6)

OR

Implement the following function using a multiplexer having two select lines A and B.

F(4 fl,C,>) = Xffl(l> 3,5, 6,9,11,13, 15).    (6)

Construct a 5><32 decoder with four 3><8 decoders and a 2X4 decoder. (6)

For three - inputs, prove that Exclusive - OR function and Equivalence function, both are same.

Design a Synchronous counter using D-flip flops for the following binary sequence:

0, 1, 3, 7, 6, 4 and repeat.    (8)

Design a 4 - bit, Mode - controlled Bidirectional shift register using SR flip flops and explain its working in both directions.    (8)

b)

a)

b)


OR

Design an asynchronous Decade Counter. Explain the steps of designing and draw its state diagram also.    (8)

Reduce the state - table given below and draw the state - diagram for reduced

(4)


table.

Present

Next State

Output

State

x -

0 x = 1

' x =

0 x = 1

a

a

b

0

0

b

c

d

0

0

c

a

d

0

0

d

e

f

0

1

e

a

f

0

1

f

g

f

0

1

g

a

f

0

1

c)

(4)


given below. What is the function of the circuit.

CP


3E2075    (4)







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