Biju Patnaik University of Technology 2008-6th Sem B.Tech (B Tech),ester computer architecture and organization -2 . - Question Paper
BPUT(B Tech),6th semester computer architecture and organization -2 ques. paper.
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Sixth Semester Examination - 2008 COMPUTER ARCHITECTURE AND ORGANIZATION - II Full Marks -70
Time: 3 Hours
Answer Question No, 1 which is compulsory and any five from the rest.
The figures in the right-hand margin indicate marks.
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1
Answer the following questions : 2x10
(a) Why GPR based machines are most widely used ?
(b) Differentiate between RISC and CISC machines.
(c) What do you understand by quantitative principle of computer design ?
(d) What do you mean by interleaved memory organization ?
(e) Why does pipelining improve performance ?
(f) Why does increasing ihe capacity and associating of a cache generally tend to increase its hit rats ?
(g) What is the use of pipeline reservation tables ?
(h) LJstdown various instruction hazards,
(i) Write at least four differences between a multiprocessor and multicomputer system.
(j) Why the performance of a parallel computer is improved by using a two level cache memory ?
2. Derive expressions for the three different performance measures of a pipeEined unit in terms of the number of stages K, number of jobs/ tasks n., and the pipeline cycle time T, Compute each of these measures for a 4-stage pipeline having delays of 15ns, 25ns, 45ns, and 30ns in the different stages while processing 100 jobs. Assume a latch delay of 5 ns. 10
3. (a) What is an llliac recirculating network ? How
it is different from barrel shifter ? Explain.
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(b) Answer the following with respect to Itliac and barrel shifter network assuming 16 PEs in each; 6
(i) Find the nu mber of nearest neighbors in each of the networks.
(ii) What is the condition for which both the networks are identical ?
4. (a) What are the different pipeline hazards ?
How do they affect the speedup ? 5
(b) Identify the data hazards while executing the following instruction in DLX pipeline. Draw the forwarding path to avoid the hazard. 5
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ADD R1T R2, R3
SUBR4tR1,R5
ANDR6.R1.R7
ORR8.R1.R9
xorrio,ri1rh
5t (a) What are the different techniques adopted to reduce miss penalty ? 5
(b) What are vector length and vector stride ? Explain with example. 5
5, What kind of parallelism is exploited in each of the following parallel architectures ? 10
(j) Pipeline Computers
(ii) Array Processors
(iii) MtMD Architectures.
7, How do tightly coupled system differs from loosly coupled ones ? Explain how intra and interprocessor communication take place in a non-hierarchical loosly coupled system ? 10
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6. (a) Representthe following program segment
in the form of a data flow graph : 5
For i = 1 to m do begin c(i) = 0
For j = 1 to n do c(i) = c(i) + a{i, h)*b(j)
end.
(b) Explain the advantages of dynamic D FCs over static DFCs, 5
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