Biju Patnaik University of Technology 2008-5th Sem B.Tech (B Tech) computer architecture- 1 . - Question Paper
BPUT(B Tech) fifth semester computer architecture- one ques. paper.
Total number of printed pages - 7 a. Tech
BCSE33QGBCSE33G3
Fifth Semester Examination - 2008
COMPUTER ARCHITECTURE AND ORGANIZATION/-!
Full Marks-70
Time-3 Hours
IWL
Answer Question No. 1 which is compulsory and any five from the rest.
The figures in the right-hand margin indicate marks.
Answer all questions : 2x10
(a) Write the basic difference between computer architecture and computer organization.
(b) What do yw by ms:ructon format *> tc) Whal ts a BUS * E*p!aJn I/O bs of a
Computer
|dj increasing (he number d atfdfessg modes improve the fQxibtoty writing as&mby language programs txit ro&ices the performance Justify
(e) What program features justifies too use o# cache memory <n a tiofarthea) momory system 7
(f) Explain the advantages and disadvantages
ol using microprogram and hardwired control unit,
(g) Which1 register in, CPU is responsible for
*
sequencing the control of execution ? 8CSE 3309/9CSE 3303 2 Contd.
Wme its iole vrtien a, branch instruction ts encourtered durmg execution.
Write !he steps to retneve a word tram a memory location by the CPU.
fO Oiiftereniiate between page fault and cache imss.
(j) How an tntenrupt service routine differs ffOiri subroutine used in high level language programs 7
IWL
2 (a) Explain In brief the Von Neumann architecture with a neat sketch. 5
(b) Gie the advantages and disadvantages of single-bus and multi'buS'organization,
5
BCSE J309/BCSE 3303 3 PT0-
3 (a) Explain the dtHereni memory device cfcaracte'scs 5
fbi Explain the Slewing 5
(j) LocaMy Q1 fCfcfGftCG
(n) Thrashing
(m) Address mapping
4. (a) Explain tfx? deference beiv.een bus artstra-iron using da >sy-chaining, poking ana independent rsGueslmg ExpSain vviih schematic diagram S
(b) What do you mean by a cache hkt cache
hit liniG and cache miss penally ? List
and briefly explain the techniques used lo
improve each ol this. 5
BCSE 3309/SC SE 3303 4 Contd,
5 i(a) Justify the use of a hierarchical memory
system f 5
(&'/ What do you understand by virtual1 memory ** Distinguish between paging and segmenabons. 5
6 (a) A CPU has *6 registers, an ALU with 16
logic and arithmetic functions and a shiher with 8 operations, all connected with a common bus system. 5
IWL
(0 Formulate a control word to specify the various microoperations lor,the CPU.
(ii) Specify the 'number of bits for each field and give a general encoding scheme for each.
BCSE3309/BCSE3303 5 p-T-0.
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(iii) Show the bits of a control word | |||
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8 that specify the microoperatin |
Write notes on any two : |
5x2 | |
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R7-R1+R14. |
(a) 8-bit microprocessors | ||
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(b) |
Design a 7-bit Combinational circuit incrementer for a microprogram sequencer. 5 |
(b) Types of Instructions (c} IEEE754S. | |
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7. (a) |
Write the Sooths Algorithm for multiplying | ||
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two binary numbers in signed-2fs ment representation. Give a flow chart | |||
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- | |||
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4 |
scheme. 5 | ||
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<b) |
Describe the addition and subtraction process of two decimal numbers in signed-magnitude representation. Suggest a scheme for hardware implementation. | ||
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0 BC5E 3309/BCSE 3303 6 Conte.' |
BCSE 3309/BCSE 3303 7 |
-C | |
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Attachment: |
| Earning: Approval pending. |
