Anna University Coimbatore 2010 B.E Information Technology 080250011-computer organization and architecture - Question Paper

ANNA UNIVERSITY COIMBATORE
B.E./B.TECH. DEGREE EXAMINATIONS: MAY/JUNE 2010
REGULATIONS: 2008
4th SEMESTER: info TECHNOLOGY
080250011-COMPUTER ORGANIZATION AND ARCHITECTURE
TIME: three Hours Max.Marks:100
PART-A
(20*2=40 Marks)
ans ALL ques.
1.Mention the registers used for communication ranging from processor and man memory.
2. Compare CSIC and Risc with respect to complexity.
3. provide an example on Index addressing mode.
4. What is meant by straight line sequencing?
5. How to transfer the contents of register R1 register R4.
6. Write the features of multiple bus organization.
7. Write a micro routine for executing the instruction on negative.
8. Write any 2 advantages of using Nano programming?
9. Mention the data hazards that occur during pipeline operation.
10. What role the Cache memory can perform in pipeline implementation.
11. elaborate the factors considered for deciding the number of pipeline stages in a system?
12. What is the meant by memory interleaving?
13. How learn and write operation is performed in static memory.
14. Differentiate write-through and write-back update methods in cache memory.
15. Write the function of translation look a side buffer.
16. How to handle miss penalties in a memory subsystem.
17. What is the difference ranging from a subroutine and interrupt service routine?
18. Sate the importance of DMA in networks.
19. Write the function of bus arbiter in DMA interface.
20. elaborate the advantages of using USB based devices.


PART-B
(5*12=60 Marks)
ans ANY 5 ques.
21. Register R5 in a program is used to point to the top of stack. Write a sequence of instruction
using indexed, auto increment and auto decrement addressing modes to perform every of the
subsequent tasks:
i) Pop the top 2 items off the stack, add them, and then push the outcome on to attack.
ii) Copy the 5th item from the top into register R3.
iii) Remove the top ten items from the stack.
22. Write note on: micro program sequencing and wide branch addressing.
23. a) explain the influence of pipelining in designing the instruction set with an example (6)
b) discuss the data dependency concept in pipelining environment. (6)
24. a) discuss the address translation mechanism of virtual memory with suitable diagram (6)
b) discuss the features and characteristics of semiconductor RAM memory. (6)
25. a) A block-set-associative cache consists of a total of 64 blocks divided into 4 block sets.
The main memory contains 4096 blocks, every consisting of 128 words (8)
i) How many bits are there in a main memory address?
ii) How many bits are there in every of the TAG, SET and WORD fields?
b) explain the limitations on associative memories(4)
26. a) explain the features and function of SCSI bus(8)
b) Illustrate the handshake control of data transfer in asynchronous bus (4)
27. discuss the bus arbitration mechanism in DMA interface.
28. explain the exception handling mechanisms when pipelining is implemented in the system.
Trace using a suitable example.

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Earning:   Approval pending.