B.Tech-B.Tech Electronics and Communications Engineering 7th Sem 7EC5 VLSI Design 7E4048(Rajasthan Technical University-2011)

7E4048
B. Tech. VII Semester (MainfBack) Examination, Nov-Dec - 2011
Electronics & Communication Engineering
7EC5 VLSI Design

Time : 3 Hours
Maximum Marks: 80
Min. Passing Marks : 24

 

 

Unit - I

 

Q.1. a) Draw the MOS transistor circuit modal. Give the justification.for all capacitance. Compare the different capacitance. Explain in detail for overloop capacitance.     [12]

b) Write and explain equation for V-I relationship of MOS transistor.    [4]

OR

Q.1 . a) Draw and explain various step involved in n-well CMOS fabrication.            [8]

b) Write comparative discussion of 'Twin-tub CMOS fabrication' and 'Siliconon - insulator' fabrication process.        [8]

 

 

Unit- II

 

 

Q.2. a) What are various second order effect? Explain how V-I characteristics modify with channel length modulation effect? Show it on V-I characteristics and in V-I relation.            [10]

b) What is body effect? Write equations related to body effect threshold voltage.         [6]

OR

Q.2. a) Calculate the V_TO NMOS, Given that V_SB=0, ni=1.45xl0¹⁰, N_A =10¹⁶ N_D (gate) = 2x10²⁰. Gate electrode is polysilicon tox = 500A. (Oxide thickness Qox = 4x10¹⁰ ), here Cox static charge.          [10]

b) Explain the influence of β_∏/β_p ratio on CMOS inverter DC transfer characteristic.       [6]

 

 

Unit - III

 

 

Q.3. a) Why does NMOS transistor produces strong '0' and weak '1' while PMOS transistor produces strong 'l' and weak '{}'?          [8]

b) Explain working of transmission gate or pass transistor. What are advantages and disadvantages of transmission gate.                       [8]

OR

Q.3. a) Design the following CMOS logic

i) Y = A+BC+DE 

ii) Y = AB+AB                                                                                                                         [8]

b) Explain and derive the expression for dynamic power dissipation of CMOS circuit.                 [8]

 

 

Unit - IV

 

 

Q.4. a) Draw the stick diagram for

i) CMOS EX-OR Gate

ii) 2:1MUX                                                                           [10]

b) Explain different types of layout design rules.                       [6]

OR

4. a) Draw the physical layout for X = ab + CD                      [8]

b) Design layout for an n-diffwire connected to p-diff wire.      [8]

 

 

Unit - V

 

 

Q.5. a) Write VHDL code for half adder by following modelling style.        [12]

i) Dataflow

ii) Behavioral

iii) Structural

b) Write VHDL code for J-K flip-flop.                                                          [4]

OR

Q.5.a) Write VHDL code for 3-bit counter.                                                           [4]

b) Write short notes on any Three offollowing. With references to the VHDL.

i) Process statement

ii) Test-bench

iii) Types of delay

iv) Advantages and limitation of VHDL.                                                                 [12]

Earning:  ₹ 4.45/-