M.Sc-M.Sc Electronics ELECTRONICS PAPER—EL-2204(Vidyasagar University, Midnapore, West Bengal-2011)

M.Sc. 2011 4th Semester Examination ELECTRONICS PAPER—EL-2204 Full Marks : 40 Time : 2 Hours The Figures in the right-hand margin indicate full marks. Candidates are required to give their answers in their own words as far as practicable. Illustrate the answers wherever necessary. Answer Q. No. 1 and any three from the rest. 1. Answer any five questions : 2x5 (a) What do you mean by the X -based design rules for the layout of VLSI circuits ? (b) Why is silane more often used for poly-silicon deposition than silicon chloride? (c) Mention the features that must be considered for metallization in VLSI. (d) Why do you require a twin-tub process in a CMOS fabrication? (e) What Is the most important practical electrical design problem in IC packages ? How is the problem reduced ? (f) State the merits and demerits of contact printing method. (Tarn Over)  2. (a) Describe with a schematic diagram an ion implantation system. (b) What are the problems involved in an ion implantation ? How can they be solved ? 5+(3+2) 3. (a) Explain different methods of etching in VLSI technology. (b) How can Si02 layers, and A1 and Al-alloy films be etched out ? (c) The electron densities in a reactive ion etching (HIE) system and high-density plasma (HDP) system range from 109 - 10*° and 101* - 1012 cm"5, respectively. Assuming the RIE chamber pressure is 200m Torr and HDP chamber pressure is 5m Torr, calculate the ionization efficiency in RIE reactors and HDP reactors at room temperature. 4+(l£+l£)+3 4. (a) Discuss the diagrams the steps followed in the fabrication of an n-channel depletion MOSFET. (b) How is the threshold voltage of a MOSFET controlled ? (c) Compare among bipolar, CMOS and BiCMOS technologies. 5+2+3 5. (a) Draw the schematic diagram of a three-phase CCD with overlapping electrodes. Explain its operation v/ith potential wells and change distribution, (b) Discuss the importance of the buried channel CCD. (3+5)+2 6. (a) What are the criteria to be fulfilled for a good package design in VLSI technology? (b) Explain different chip-to-package interconnection techniques used in VLSI. (c) What do you mean by the functional yield and parametic yield ? 2+5+(I j + 1 C/11 /M.Sc./4"' Seme./EL~2204

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