Other Bachelor Degree- DIGITAL PRINCIPLES AND SYSTEM DESIGN (Karunya University, Coimbatore-2010)
Saturday, 24 August 2013 04:42anudouglas
Karunya University
(Karunya Institute of Technology and Sciences)
(Declared as Deemed to be University under Sec.3 of the UGC Act, 1956)
End Semester Examination – November/December 2010
Subject Title: DIGITAL PRINCIPLES AND SYSTEM DESIGN Time: 3 hours
Subject Code: 09IT204 Maximum Marks: 100
Answer ALL questions
PART – A (10 x 1 = 10 MARKS)1. Convert (10101100)2 into octal.
2. What is the important property of XS3 code?
3. What is the drawback of a serial adder compared to parallel adder?
4. Represent (-10)10 in sign-2’s complement form.
5. Mention any two applications of multiplexers.
6. Draw the logic diagram of a 2 x 4 decoder using NAND gates.
7. Define set-up time for a negative edge triggered FF.
8. Write the excitation table of a JK FF.
9. What is the basic difference between asynchronous sequential circuits and synchronous sequential circuits?
10. What is known as fundamental mode of operation of an asynchronous sequential circuit?
PART – B (5 x 3 = 15 MARKS)
11. Write the absorption law and prove it.
12. Draw the logic diagram of a 4 bit binary to gray code converter using ex-OR gates.
13. Describe a 2 x 1 multiplexer using a HDL.
14. Write the HDL behavioral description of 4-bit universal shift register.
15. With an example explain static -1- hazard and its removal.
PART – C (5 x 15 = 75 MARKS)
16. Simplify the following Boolean function using Karnaugh map and realize the simplified function using only NAND gates.
F (a, b, c, d, e) = åm (1, 3, 4, 5, 11, 14, 15, 16, 17, 19, 20, 24, 26, 28, 30)
(OR)
17. a. Convert the following Boolean function into product of maxterms form. (8)
F (a, b, c) =
b. Show that the dual of exclusive –OR is also its complement. (7)
18. Design a single stage BCD adder and draw its block diagram.
(OR)
19. Design a 4-bit carry-look-ahead adder and draw its block diagram.
20. Design an octal to binary priority encoder and draw its logic diagram using gates.
(OR)
21. Draw the logic diagram of the realization of the following functions using a PAL device
F1 (a, b, c) = åm (1, 2, 4, 6, 7)
F2 (a, b, c) = åm (2, 4, 5, 6)
F3 (a, b, c) = åm (1, 4, 6)
[P.T.O]
22. a. Draw the block diagram of 4 bit universal shift register using FFs and multiplexers and explain its working. (12)
b. Compare a 4- bit binary counter and a 4-stage ring counter. (3)
(OR)
23. Design a synchronous modulo -5 up-down counter using JK FFs. Draw the timing diagram and write your inference.
24. a. Stage the three constraints that must be satisfied while designing an asynchronous sequential circuit to function properly. (5)
b. Explain the two types of race conditions using an example. (10)
(OR)
25. Obtain the primitive flow table and a minimum row flow table for a fundamental mode asynchronous sequential circuit with two inputs x and y, with a single output z, meeting the following requirement:
The output z is 1, only when the values of inputs x and y are same and y was the variable that changed value causing both inputs to become the same.
| Earning: ₹ 0.00/- |
