B.E-B.E Electronics and Instrumentation Engineering Fundamentals of VLSI Design(Sathyabama University, Chennai, Tamil Nadu-2010)
Friday, 23 August 2013 06:52Duraimani
(Established under section 3 of UGC Act,1956)
Course & Branch :B.E - E&C/EIE
Title of the Paper :Fundamentals of VLSI Design Max. Marks :80
Sub. Code :517702/518704/6C0093 Time : 3 Hours
Date :03/03/2010 Session :AN
PART - A (10 x 2 = 20)
Answer ALL the Questions
1. Define threshold voltage of a MOS transistor.
2. What is meant by ion implantation?
3. Draw a CMOS logic inverter using P-and N-switch.
4. Distinguish between Lamda rules and Micron rules.
5. What is a combinational circuit? Give examples.
6. What is the purpose of data path circuit? What are its building blocks?
7. What is meant by top-down and bottom-up design approach?
8. Compare Verilog with VHDL.
9. What is FPGA? Compare it with CPLD?
10. What are the programming methods for FPGA and CPLD?
PART – B (5 x 12 = 60)
Answer All the Questions
11. With diagrams and equations, explain the power dissipation characteristics of CMOS device.
(or)
12. With neat diagram explain a basic n-well CMOS process.
13. (a) Build a CMOS NAND gate and CMOS NOR gate using MOS transistor switches (P-switch and N-switch).
(b) Build a CMOS positive-level-sensitive D latch and a CMOS positive-edge-triggered D register.
(or)
14. Explain the operation of transmission gate. How does it act as a resistor?
15. (a) Explain the working of a 1-to-8 demultiplexer.
(b) Explain the working of a Master/Slave JK – FF.
(or)
16. With example and neat diagram explain the operation of a 4 x 4 – bit array combinational multiplier.
17. Draw a 4-bit ripple carry adder logic diagram and write VHDL codes in behavioral, dataflow and structural gate modeling.
(or)
18. Draw a 1-to-4 demultiplexer logic diagram and write VHDL codes in behavioral, dataflow and structural gate modeling.
19. With suitable diagram, explain FPGA architecture.
(or)
20. With block diagram, explain FPGA design flow for multiplexer.
| Earning: ₹ 3.50/- |
