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B.E-B.E Electronics and Communication Engineering Digital Systems (Sathyabama University, Chennai, Tamil Nadu-2011)

Monday, 19 August 2013 07:20Duraimani
SATHYABAMA UNIVERSITY
(Established under section 3 of UGC Act,1956)
Course & Branch :B.E - P-ECE
Title of the Paper :Digital Systems                              Max. Marks:80
Sub. Code :SECX1002 (2010-11)                                  Time : 3 Hours
Date :03/12/2011                                                            Session :FN
                                       PART - A                    (10 x 2 = 20)
                        Answer ALL the Questions
1.     Why Gray Code is called a reflective code?
2.     Expand A’ + B’ to minterms.
3.     What is a multi-level gate network?
4.     Realize f = C’+AB’+A’B using NAND gates.
5.     Draw a two bit magnitude comparator.
6.     Distinguish between a decoder and a de-multiplexer
7.     State some applications of shift registers.
8.     What is a State diagram?
9.     Why ECL logic is faster than TTL?
10.   State the parameters used to characterize logic families.

PART – B                       (5 x 12 = 60)
Answer All the Questions
11.   (a) Perform the following conversions:
                (i) A0F9.0EB16 TO DECIMAL
                (ii) 756.6038 TO HEX.
                (iii) 110101.1010102 TO OCTAL
        (b) Do the following arithmetic:
                (i) Add 6E16 and C516
                        (ii) Subtract 7B16 from C416
                        (iii) Subtract 5D16 from 3A16
(or)
12.   Discuss the properties of Boolean algebra.
13.   Reduce using  K- map both in POS and SOP forms :
        F =  ∑m (0,2,4,6,7,8,10,12,13,15)
(or)
14.   Obtain the minimal POS expression using the tabular method for: 
        f (v,w,x,y,z)  = ∑m (0,4,12,16,19,24,27,28,29,31)
15.   (a) Implement the following function with a 8 X 1 multiplexer:
                F(A,B,C,D) = ∑(1,3,4,11,12,13,14,15).  (7)
        (b) Write short notes on Priority encoder. (5)
(or)
16.   Realize a BCD adder using full adders and explain.
17.   (a) Explain the concept of master slave using two D latches and an inverter.
        (b) Brief about State reduction and State assignment.
(or)
18.   (a) Explain the four stage switch tail ring counter.
        (b) Convert a JK Flip Flop to a T Flip Flop.
19.   (a) Compare the characteristics of different logic families.  (8)
        (b) Draw the circuit diagram of a 3-input I2L NOR Gate. (4)
(or)
20.   Implement the following two functions using PLA:
                F1(A,B,C) = ∑(0,1,2,4)
                F2(A,B,C) = ∑(0,5,6,7) 
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