M.Tech-M.Tech Nanotechnology MOS Device Modeling (Sathyabama University, Chennai, Tamil Nadu-2012)
Monday, 19 August 2013 07:01Duraimani
(Established under section 3 of UGC Act,1956)
Course & Branch :M.Tech - NANO/W-VLSI
Title of the Paper :MOS Device Modeling Max. Marks:80
Sub. Code :782104-SECX5019 (2008-09-2010-2011) Time : 3 Hours
Date :02/06/2012 Session :FN
PART - A (6 x 5 = 30)
Answer ALL the Questions
1. Explain the characteristics of a MOS transistor.
2. Define the interface traps. Derive the expression for interface trapped capacitance.
3. Explain how trapped Oxide charge can be annealed out.
4. Explain the MOS device parameters in spice level 1 model.
5. Explain the principle of Monte Carlo analysis.
6. Explain how MOSFET can be used as resistors.
PART – B (5 x 10 = 50)
Answer ALL the Questions
7. Draw the energy band diagram for gate region of a MOS transistor. Also explain band bending in p-type bulk Silicon.
(or)
8. Discuss the low frequency and high frequency CV plots with necessary equations.
9. Discuss the shift in threshold voltage of pMOS and nMOS transistors due to Oxide trap change.
(or)
10. Write a short notes on (a) Radiation hardening
(b) Gate metallization
11. Derive the expression for drain current in the sub threshold region of operation for MOSFET.
(or)
12. (a) Explain the mathematical model of I-V characteristics.
(b) Discuss the effect of electric field on the carrier velocity.
13. Discuss briefly (a) Narrow width effect
(b) Hot carrier effect
(or)
14. Discuss the small signal analysis of MOSFET and explain the parameters associated with the model.
15. With a neat sketch explain the following devices: HMOS, Sy MOSFET, BESOI and VMOS and also compare these devices with conventional CMOS.
(or)
16. Write short notes on MOS device, as depletion mode device, as load.
| Earning: ₹ 5.05/- |
