M.Tech-M.Tech Embedded Systems Advanced Digital System Design(Sathyabama University, Chennai, Tamil Nadu-2012)
Friday, 09 August 2013 01:06Duraimani
(Established under section 3 of UGC Act,1956)
Course & Branch :M.Tech - EMBED/AEL/W-AEL/VLSI/W-VLSI
Title of the Paper :Advanced Digital System Design
Sub. Code :782102 (2008-2009-2010-2011)
Max. Marks:80
Time : 3 Hours
Date :29/05/201
Session :FN
PART - A (6 x 5 = 30)
Answer ALL the Questions
1. Define a sequential machine for the state table shown below. Draw the state diagram and discuss on the type of machine used.
| Present State |
Next State Output |
|
| Input |
||
| I1 |
I2 |
|
| A |
A,0 |
B,1 |
| B |
D,1 |
A,0 |
| C |
B,0 |
D,1 |
| D |
A,0 |
C,0 |
2. State the guidelines for state Assignment.
3. Implement the following Boolean function by a hazard free OR-AND network f = S(0,2,6,7).
4. Realize a parallel binary adder.
5. Discuss the relationship between state diagrams and ASM charts.
6. Explain the FPGA I/O block.
PART – B (5 x 10 = 50)
Answer ALL the Questions
7. Design an odd parity checker for serial data with one o/p and a clock and an o/p (z).
(or)
8. Find a reduced state machine that covers the machine shown below.
| Present State |
Next state o/p |
|
| I1 |
I2 |
|
| A |
D,0 |
C,1 |
| B |
E,1 |
A,1 |
| C |
H,1 |
D,1 |
| D |
D,0 |
C,1 |
| E |
B,0 |
G,1 |
| F |
H,1 |
D,1 |
| G |
A,0 |
F,1 |
| H |
C,0 |
A,1 |
| I |
G,1 |
A,1 |
(or)
10. Reduce the following state table to a minimum number of states.
| Present State |
Next State |
Present State |
||
| |
|
|
|
|
| A |
A |
E |
1 |
0 |
| B |
C |
F |
0 |
0 |
| C |
B |
H |
0 |
0 |
| D |
E |
F |
0 |
0 |
| E |
D |
A |
0 |
1 |
| F |
B |
F |
1 |
1 |
| G |
D |
H |
0 |
1 |
| H |
H |
G |
1 |
0 |
11. Design a fundamental-mode mod-2 counter using D latched and AND-OR gates for its combinational circuits. The output is to be flicker free and the combinational circuit must not contain any hazard.
(or)
12. What are cycle and races? Discuss on race-free assignments.
13. Describe the programmable logic devices.
(or)
14. Draw the ASM chart for a mod-8 binary counter and explain.
15. With a neat diagram explain Xilinx 3000 series logic block.
(or)
16. Describe in detail the system development tools for the Xilinx FPGA with its flowchart.
| Earning: ₹ 7.00/- |
