North Maharashtra University 2010 B.E Computer Science and Engineering Digital System Design, S.E, /e - Question Paper
IVIAY - JUNk ZU1U
Mx. Marks: 100
UNIT-1
*
i
I. A) Design a combinational circuit that converts 4-bft gray code
ff
Tt'
to 4-bit binary no. 10
B) A combinational circuit is to be designed (hot has one control line and three data lines When control bne ts tow circuit ihould detect whether two of <ftrta lines air simultaneously high. When aootrol tae is tagb outpi* a km 10 O tmpfcment 32x1 MUX with two 16 x I and one 2 x 1 Ml/X. It
_ V
UNIT-II
2. A) Implement ft im(0.1.3*4,7) and f," p (2,3,6,7)
Hf
It
10
unngROM
B) Design l~btt binary exceai 3 uatng PLA
O bnpkment foil stale diagram uaingPAl.*peafyaue of PAL It
UNIT *111
A) Design * divide by 12 counter using S-RfhpOop if
B> A Hate tabk of sequential circuit with one input x a
below. Reduce the same upto S ftates ami design the
circuit uring J-K (lip flop 19
ro
NS O/P *0
B.O
0,0
0,0
H,0
0,0
,L
0,0
H.O
H
C
D
F
O
H
C) Design a decade counter using D flip flop.
UNIT-IV
10
A) Design sequential circuit uaing J-K flip flop.
10
a
|
00,01,10/11 |
 |
|
00.01.10/10 |
B) Design a sequential cvcurt by foil next state aquaM uv*
J-K flip flop where x and y arc input A, x AB y KC ay B, - x AO y BC z xB AB
Ofctun logic diagnaiwtoMMealaMe, Ms table sad
10
state diagram
O Dcaign a sequential circuit wMh two D flip flop A and B d one input jl When x - 0, the state of the circuit fMnaam sne where as when x * 1 the circuit got* to le tonsttion from 00 to 01 to 11 to 10 and back to 00
10
|
UNIT V |  |
y A) Implement ASM chwt by traditional method
:2
V*
. I* i
 |
|
.* * |
/
|
m. .fiTW'/ .. * a A'iyv *?* ** ' * | |
 |
A->/ |
a ,
B) Design the ASM chart uaii* MVX cxuftolier
below where X| And x2 ire input and z t*output ind
... <&
using traditional mefb
C)
 |
|
|
Attachment: |
| Earning: Approval pending. |
