Noorul Islam University 2009 Diploma Computer Science and Technology Cs1302 computer networks - Question Paper
This ques. bank consists important ques. about data communication and networks.
NOORUL ISLAM COLLEGE OF ENGINEERING, KUMARACOIL.
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
CS1302 COMPUTER NETWORKS
PART A UNIT - I DATA COMMUNICATION 1. What is mean by data communication?
Data communication is the exchange of data (in the form of 1s and 0s) between two devices via some form of transmission medium (such as a wire cable).
2. What are the three criteria necessary for an effective and efficient network?
The most important criteria are performance, reliability and security.
Performance of the network depends on number of users, type of transmission medium, the capabilities of the connected h/w and the efficiency of the s/w.
Reliability is measured by frequency of failure, the time it takes a link to recover from the failure and the networks robustness in a catastrophe.
Security issues include protecting data from unauthorized access and viruses.
3. What are the three fundamental characteristics determine the effectiveness of the data communication system?
The effectiveness of the data communication system depends on three fundamental characteristics:
Delivery: The system must deliver data to the correct destination.
Accuracy: The system must deliver data accurately.
Timeliness: The system must deliver data in a timely manner.
4. What are the advantages of distributed processing?
Advantages of distributed processing include security/encapsulation, distributed databases, faster problem solving, security through redundancy and collaborative processing.
In networks, communication occurs between the entities in different systems. Two entities cannot just send bit streams to each other and expect to be understood. For communication, the entities must agree on a protocol. A protocol is a set of rules that govern data communication.
Co-ordination across the nodes of a network is necessary for an efficient communication. If there are no standards, difficulties arise. A standard provides a model or basis for development to which everyone has agreed.
7. For n devices in a network, what is the number of cable links required for a mesh and ring topology?
Mesh topology - n (n-1)/2 Ring topology - n
8. What is the difference between a passive and an active hub?
An active hub contains a repeater that regenerates the received bit patterns before sending them out. A passive hub provides a simple physical connection between the attached devices.
9. Distinguish between peer-to-peer relationship and a primary-secondary relationship.
Peer-to-peer relationship: All the devices share the link equally. Primary-secondary relationship: One device controls traffic and the others must transmit through it.
10. Assume 6 devices are arranged in a mesh topology. How many cables are needed? How many ports are needed for each device?
Number of cables=n (n-1 )/2=6(6-1 )/2=15 Number of ports per device=n-1 =6-1=5
11. Group the OSI layers by function.
The seven layers of the OSI model belonging to three subgroups. Physical, data link and network layers are the network support layers; they deal with the physical aspects of moving data from one device to another. Session, presentation and application layers are the user support layers; they allow interoperability among unrelated software systems. The transport layer ensures end-to-end reliable data transmission.
12. What are header and trailers and how do they get added and removed?
Each layer in the sending machine adds its own information to the message it receives from the layer just above it and passes the whole package to the layer just below it. This information is added in the form of headers or trailers. Headers are added to the message at the layers 6,5,4,3, and 2. A trailer is added at layer2. At the receiving machine, the headers or trailers attached to the data unit at the corresponding sending layers are removed, and actions appropriate to that layer are taken.
13. The transport layer creates a communication between the source and destination. What are the three events involved in a connection?
Creating a connection involves three steps: connection establishment, data transfer and connection release.
Direct current is a zero-frequency signal with constant amplitude.
15. How does NRZ-L differ from NRZ-I?
In the NRZ-L sequence, positive and negative voltages have specific meanings: positive for 0 and negative for 1. in the NRZ-I sequence, the voltages are meaningless. Instead, the receiver looks for changes from one level to another as its basis for recognition of 1s.
16. Using HDB3, encode the bit stream 10000000000100. Assume the number of 1s so far is odd and the first 1 is positive.
1 0 0 0 0 0 0 0 0 0 0 1 0 0 Amplitude
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17. What are the functions of a DTE? What are the functions of a DCE? Data terminal equipment is a device that is an information source or an information sink. It is connected to a network through a DCE. |
Data circuit-terminating equipment is a device used as an interface between a DTE and a network.
18. What does the electrical specification of EIA-232 describe?
The electrical specification of EIA-232 defines that signals other than data must be sent using OFF as less than -3 volts and ON as greater than +3 volts. The data must be transmitted using NRZ-L encoding.
19. Discuss the mode for propagating light along optical channels.
There are two modes for propagating light along optical channels, multimode and single mode.
Multimode: Multiple beams from a light source move through the core in different paths. Single mode: Fiber with extremely small diameter that limits beams to a few angles, resulting in an almost horizontal beam.
The phenomenon related to the bending of light when it passes from one medium to another.
UNIT-II DATA LINK LAYER 1.What are the responsibilities of data link layer?
Specific responsibilities of data link layer include the following.
a) Framing
b) Physical addressing
c) Flow control
d) Error control
e) Access control
2. Mention the types of errors.
There are 2 types of errors
a) Single-bit error.
b) Burst-bit error.
3. Define the following terms.
Single bit error: The term single bit error means that only one bit of a given data unit (such as byte character/data unit or packet) is changed from 1 to 0 or from 0 to 1.
Burst error: Means that 2 or more bits in the data unit have changed from 1 to 0 from
0 to 1.
It is the error detecting mechanism, which means a shorter group of bits or extra bits may be appended at the destination of each unit.
5. List out the available detection methods.
There are 4 types of redundancy checks are used in data communication.
a) Vertical redundancy checks (VRC).
b) Longitudinal redundancy checks (LRC).
c) Cyclic redundancy checks (CRC).
d) Checksum.
The most common and least expensive mechanism for error detection is the vertical redundancy check (VRC) often called a parity check. In this technique a redundant bit
called a parity bit, is appended to every data unit so, that the total number of 0s in the unit (including the parity bit) becomes even.
In longitudinal redundancy check (LRC), a block of bits is divided into rows and a redundant row of bits is added to the whole block.
The third and most powerful of the redundancy checking techniques is the cyclic redundancy checks (CRC) CRC is based on binary division. Here a sequence of redundant bits, called the CRC remainder is appended to the end of data unit.
9. Write short notes on CRC generator.
A CRC generator uses a modulo-2 division.
In the first step, the 4-bit divisor is subtracted from the first 4 bit of the
dividend.
Each bit of the divisor is subtracted from the corresponding bit of the dividend without disturbing the next higher bit.
10. Write short notes on CRC checker.
A CRC checker functions exactly like a generator. After receiving the data appended with the CRC it does the same modulo-2 division. If the remainder is all 0s the CRC is dropped and the data accepted. Otherwise, the received stream of bits is discarded and the dates are resent.
11. Give the essential properties for polynomial.
A polynomial should be selected to have at least the following properties.
a) It should not be
b) It should be divisible by(x+1).
The error detection method used by the higher layer protocol is called checksum. Checksum is based on the concept of redundancy.
13. What are the steps followed in checksum generator?
The sender follows these steps
a) The units are divided into k sections each of n bits.
b) All sections are added together using 2s complement to get the sum.
c) The sum is complemented and become the checksum.
d) The checksum is sent with the data.
14. List out the steps followed is checksum checker side.
The receiver must follow these steps
a) The unit is divided into k section each of n bits.
b) All sections are added together using 1 s complement to get the sum.
c) The sum is complemented.
d) If the result is zero.
15. Write short notes on error correction.
It is the mechanism to correct the errors and it can be handled in 2 ways.
a) When an error is discovered, the receiver can have the sender retransmit the entire data unit.
b) A receiver can use an error correcting coder, which automatically corrects certain errors.
16. Mention the types of error correcting methods.
There are 2 error-correcting methods.
a) Single bit error correction
b) Burst error correction.
17. What is the purpose of hamming code?
A hamming code can be designed to correct burst errors of certain lengths. So the simple strategy used by the hamming code to correct single bit errors must be redesigned to be applicable for multiple bit correction.
Flow control refers to a set of procedures used to restrict the amount of data. The sender can send before waiting for acknowledgment.
Each receiving device has a block of memory called a buffer, reserved for storing incoming data until they are processed.
20. Mention the categories of flow control.
There are 2 methods have been developed to control flow of data across communication links.
a) Stop and wait- send one from at a time.
b) Sliding window- send several frames at a time.
UNIT III NETWORK LAYER
1. What are the network support layers and the user support layers?
Network support layers:
The network support layers are Physical layer, Data link layer and Network layer. These deals with electrical specifications, physical connection, transport timing and reliability.
User support layers:
The user support layers are: Session layer, Presentation layer, Application layer. These allow interoperability among unrelated software system.
2. With a neat diagram explain the relationship of IEEE Project to the OSI model?
Other layers
Other layers
Network
Network
Logical Link Control Media Access Control
Data link
IEEE
into
The
layer
Physical
Physical
link
has subdivided the data two sub layers:
* Logical link control (LLC)
* Medium access control (MAC)
LLC is non-architecture specific. The MAC sub layer contains a number of distinct modules, each carries proprietary information specific to the LAN product being used.
3. What are the functions of LLC?
The IEEE project 802 models takes the structure of an HDLC frame and divides it into 2 sets of functions. One set contains the end user portion of the HDLC frame - the
logical address, control information, and data. These functions are handled by the IEEE 802.2 logical link control (LLC) protocol.
4. What are the functions of MAC?
MAC sub layer resolves the contention for the shared media. It contains synchronization, flag, flow and error control specifications necessary to move information from one place to another, as well as the physical address of the next station to receive and route a packet.
5. What is protocol data unit?
The data unit in the LLC level is called Protocol Data Unit (PDU). It contains four
fields.
Destination Service Point Address (DSAP)
Source Service Access Point
Control field
Information field
DSAP SSAP Control Information
6. What are headers and trailers and how do they get added and removed?
The control data added to the beginning of a data is called headers. The control data added to the end of a data is called trailers. At the sending machine, when the message passes through the layers each layer adds the headers or trailers. At the receiving machine, each layer removes the data meant for it and passes the rest to the next layer.
7. What are the responsibilities of network layer?
The network layer is responsible for the source-to-destination delivery of packet across multiple network links. The specific responsibilities of network layer include the following:
Logical addressing.
Routing.
A logical circuit made between the sending and receiving computers. The connection is made after both computers do handshaking. After the connection, all packets follow the same route and arrive in sequence.
In datagram approach, each packet is treated independently from all others. Even when one packet represents just a place of a multipacket transmission, the network treats it although it existed alone. Packets in this technology are referred to as datagram.
10. What are the two types of implementation formats in virtual circuits?
Virtual circuit transmission is implemented in 2 formats.
Switched virtual circuit
Permanent virtual circuit.
11. What is meant by switched virtual circuit?
Switched virtual circuit format is comparable conceptually to dial-up line in circuit switching. In this method, a virtual circuit is created whenever it is needed and exits only for the duration of specific exchange.
12. What is meant by Permanent virtual circuit?
Permanent virtual circuits are comparable to leased lines in circuit switching.
In this method, the same virtual circuit is provided between two uses on a continuous basis. The circuit is dedicated to the specific uses.
Routers relay packets among multiple interconnected networks. They Route packets from one network to any of a number of potential destination networks on Internet routers operate in the physical, data link and network layer of OSI model.
14. What is meant by hop count?
The pathway requiring the smallest number of relays, it is called hop-count routing, in which every link is considered to be of equal length and given the value one.
15. How can the routing be classified?
The routing can be classified as,
Adaptive routing
Non-adaptive routing.
16. What is time-to-live or packet lifetime?
As the time-to-live field is generated, each packet is marked with a lifetime, usually the number of hops that are allowed before a packet is considered lost and accordingly, destroyed. The time-to-live determines the lifetime of a packet.
A brouter is a single protocol or multiprotocol router that sometimes act as a router and sometimes act as a bridge.
18. Write the keys for understanding the distance vector routing.
The three keys for understanding the algorithm are
Knowledge about the whole networks
Routing only to neighbors
Information sharing at regular intervals
19. Write the keys for understanding the link state routing.
The three keys for understanding the algorithm are
Knowledge about the neighborhood.
Routing to all neighbors.
Information sharing when there is a range.
20. How the packet cost referred in distance vector and link state routing?
In distance vector routing, cost refer to hop count while in case of link state routing, cost is a weighted value based on a variety of factors such as security levels, traffic or the state of the link.
UNIT IV TRANSPORT LAYER 1. What is function of transport layer?
The protocol in the transport layer takes care in the delivery of data from one application program on one device to an application program on another device. They act as a link between the upper layer protocols and the services provided by the lower layer.
2. What are the duties of the transport layer?
The services provided by the transport layer End-to- end delivery Addressing Reliable delivery Flow control Multiplexing
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3. What is the difference between network layer delivery and the transport layer delivery?_ | ||||
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4. What are the four aspects related to the reliable delivery of data? |
The four aspects are,
Error control Sequence control Loss control Duplication control
At the sending and receiving end of the transmission, TCP divides long transmissions into smaller data units and packages each into a frame called a segment.
6. What is meant by segmentation?
When the size of the data unit received from the upper layer is too long for the network layer datagram or data link layer frame to handle, the transport protocol divides it into smaller usable blocks. The dividing process is called segmentation.
7. What is meant by Concatenation?
The size of the data unit belonging to single sessions are so small that several can fit together into a single datagram or frame, the transport protocol combines them into a single data unit. The combining process is called concatenation.
8. What are the types of multiplexing?
The types of multiplexing are,
Upward multiplexing Downward multiplexing
9. What are the two possible transport services?
Two basic types of transport services are,
Connection service Connectionless services
10. The transport layer creates the connection between source and destination. What are the three events involved in the connection?
For security, the transport layer may create a connection between the two end ports. A connection is a single logical path between the source and destination that is associated with all packets in a message. Creating a connection involves three steps:
Connection establishment
Data transfer & Connection release.
11. What is meant by congestion?
Congestion in a network occurs if user sends data into the network at a rate greater than that allowed by network resources.
12. Why the congestion occurs in network?
Congestion occurs because the switches in a network have a limited buffer size to store arrived packets.
13. What is meant by quality of service?
The quality of service defines a set of attributes related to the performance of the connection. For each connection, the user can request a particular attribute each service class is associated with a set of attributes.
14. What are the two categories of QoS attributes?
The two main categories are User Oriented Network Oriented
15. List out the user related attributes?
User related attributes are
SCR - Sustainable Cell Rate
PCR - Peak Cell Rate
MCR- Minimum Cell Rate
CVDT - Cell Variation Delay Tolerance
16. What are the networks related attributes?
The network related attributes are,
Cell loss ratio (CLR)
Cell transfer delay (CTD)
Cell delay variation (CDV)
Cell error ratio (CER)
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17. What is the difference between service point address, logical address and physical address? __ | ||||||
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17. What are the rules of nonboundary-level masking?
The bytes in the IP address that corresponds to 255 in the mask will be repeated in the subnetwork address
The bytes in the IP address that corresponds to 0 in the mask will change to
0 in the subnetwork address
For other bytes, use the bit-wise AND operator
A device used to connect two separate networks that use different communication protocols.
In link state routing, a small packet containing routing information sent by a router to all other router by a packet called link state packet.
UNIT - V APPLICATION LAYER 1. What is the purpose of Domain Name System?
Domain Name System can map a name to an address and conversely an address to name.
2. Discuss the three main division of the domain name space.
Domain name space is divided into three different sections: generic domains, country domains & inverse domain.
Generic domain: Define registered hosts according to their generic behavior, uses generic suffixes.
Country domain: Uses two characters to identify a country as the last suffix.
Inverse domain: Finds the domain name given the IP address.
3. Discuss the TCP connections needed in FTP.
FTP establishes two connections between the hosts. One connection is used for data transfer, the other for control information. The control connection uses very simple rules of communication. The data connection needs more complex rules due to the variety of data types transferred.
4. Discuss the basic model of FTP.
The client has three components: the user interface, the client control process, and the client data transfer process. The server has two components: the server control process and the server data transfer process. The control connection is made between the control processes. The data connection is made between the data transfer processes.
5. What is the function of SMTP?
The TCP/IP protocol supports electronic mail on the Internet is called Simple Mail Transfer (SMTP). It is a system for sending messages to other computer users based on e-mail addresses. SMTP provides mail exchange between users on the same or different computers.
6. What is the difference between a user agent (UA) and a mail transfer agent (MTA)?
The UA prepares the message, creates the envelope, and puts the message in the envelope. The MTA transfers the mail across the Internet.
7. How does MIME enhance SMTP?
MIME is a supplementary protocol that allows non-ASCII data to be sent through SMTP. MIME transforms non-ASCII data at the sender site to NVT ASCII data and deliverers it to the client SMTP to be sent through the Internet. The server SMTP at the receiving side receives the NVT ASCII data and delivers it to MIME to be transformed back to the original data.
8. Why is an application such as POP needed for electronic messaging?
Workstations interact with the SMTP host, which receives the mail on behalf of every host in the organization, to retrieve messages by using a client-server protocol such as Post Office Protocol, version 3(POP3). Although POP3 is used to download
messages from the server, the SMTP client still needed on the desktop to forward messages from the workstation user to its SMTP mail server.
9. Give the format of HTTP request message.
Request Line
Headers
A Blank Line
Body (present only in some messages)
10. Give the format of HTTP response message.
Status Line
Headers
A Blank Line
Body (present only in some messages)
11. Write down the three types of WWW documents.
The documents in the WWW can be grouped into three broad categories: static, dynamic and active.
Static: Fixed-content documents that are created and stored in a server.
Dynamic: Created by web server whenever a browser requests the document.
Active: A program to be run at the client side.
12. What is the purpose of HTML?
HTML is a computer language for specifying the contents and format of a web document. It allows additional text to include codes that define fonts, layouts, embedded graphics and hypertext links.
CGI is a standard for communication between HTTP servers and executable programs. It is used in crating dynamic documents.
14. Name four factors needed for a secure network.
Privacy: The sender and the receiver expect confidentiality.
Authentication: The receiver is sure of the senders identity and that an imposter has not sent the message.
Integrity: The data must arrive at the receiver exactly as it was sent.
Non-Reputation: The receiver must able to prove that a received message came from a specific sender.
15. How is a secret key different from public key?
In secret key, the same key is used by both parties. The sender uses this key and an encryption algorithm to encrypt data; the receiver uses the same key and the corresponding decryption algorithm to decrypt the data.
In public key, there are two keys: a private key and a public key. The private key is kept by the receiver. The public key is announced to the public.
16. What is a digital signature?
Digital signature is a method to authenticate the sender of a message. It is similar to that of signing transactions documents when you do business with a bank. In network transactions, you can create an equivalent of an electronic or digital signature by the way you send data.
17. What are the advantages & disadvantages of public key encryption? Advantages:
a) Remove the restriction of a shared secret key between two entities. Here each entity can create a pair of keys, keep the private one, and publicly distribute the other one.
b) The no. of keys needed is reduced tremendously. For one million users to communicate, only two million keys are needed.
Disadvantage:
If you use large numbers the method to be effective. Calculating the cipher text using the long keys takes a lot of time. So it is not recommended for large amounts of text.
18. What are the advantages & disadvantages of secret key encryption? Advantage:
Secret Key algorithms are efficient: it takes less time to encrypt a message. The reason is that the key is usually smaller. So it is used to encrypt or decrypt long messages. Disadvantages:
a) Each pair of users must have a secret key. If N people in world want to use this method, there needs to be N (N-1)/2 secret keys. For one million people to communicate, a half-billion secret keys are needed.
b) The distribution of the keys between two parties can be difficult.
Permutation is transposition in bit level.
Straight permutation: The no. of bits in the input and output are preserved. Compressed permutation: The no. of bits is reduced (some of the bits are dropped). Expanded permutation: The no. of bits is increased (some bits are repeated).
20. Define substitutional & transpositional encryption.
Substitutional: A character level encryption in which each character is replaced by another character in the set.
Transpositional: A Character level encryption in which the characters retain their plaintext but the position of the character changes.
PART B UNIT I Data communications 1. Explain ISO/OSI reference model.
> Physical layer
> Data link layer
> Network layer
> Transport layer
> Session layer
> Presentation layer
> Application layer
2. Explain the topologies of the network.
> Mesh topology
> Star topology
> Tree topology
> Bus topology
> Ring topology
3. Explain the categories of networks.
> Local Area Network(LAN)
> Metropolitan Area Network(MAN)
> Wide Area Network(WAN)
4. Explain coaxial cable & fiber optics.
> Coaxial cable
Coaxial cable standards
Coaxial cable connectors
> Fiber optics
Propagation modes
Fiber sizes
Cable composition
Light sources for optical cable
Fiber optic connectors
Advantages & disadvantages of optical fiber
5. Explain line coding (digital to digital conversion).
> Unipolar
DC component
Synchronization
> Polar
Non return to zero(NRZ)
NRZ-L
NRZ-I
Return to zero
Biphase
Manchester
Differential Manchester
> Bipolar
Alternate Mark Inversion(AMI)
Bipolar 8-zero substitution(B8ZS)
High-Density Bipolar 3(HDB3)
UNIT II Data link layer 1. Explain error detection and error correction techniques.
> Types of errors
Single bit error
Burst error
> Error detection
Vertical redundancy check(VRC)
Longitudinal redundancy check(LRC)
Cyclic redundancy check(CRC)
Checksum
> Error correction
Single-bit error correction
Hamming code
Burst error correction
2. Explain error control mechanism.
> Stop and wait ARQ
> Sliding window ARQ
Go back-n
Selective-reject
3. Explain the flow control mechanism
> Stop and wait
> Sliding window.
4. Explain the timers and time registers in FDDI.
Time registers
Synchronous allocation(SA)
Target token rotation time(TTRT)
Absolute maximum time(AMT)
> Timers
Token rotation timer(TRT)
Token holding timer(THT)
> Access method :CSMA/CD
> Addressing
> Electrical specification
> Frame format
> Implementation:
10 base 5 :Thick Ethernet
10 base 2 :Thin Ethernet
10 base T Twisted-pair Ethernet
1 base 5 :Star LAN
UNIT III Network layer 1. Explain the two approaches of packet switching techniques.
> Datagram approach
> Virtual circuit approach
Switched virtual circuit(SVC)
Permanent virtual circuit(PVC)
> Circuit - switched connection versus virtual - circuit connection
Path versus route
Dedicated versus shared
2. Explain IP addressing method.
> Internetwork protocol (IP)
> Datagram
> Addressing
Classes
Dotted decimal notation
A sample internet
3. Define routing & explain distance vector routing and link state routing.
> Distance vector routing
Sharing information
Routing table
Creating the table
Updating the table
Updating algorithm
> Link state routing
Information sharing
Packet cost
Link state packet
Getting information about neighbors
Initialization
Link state database
4. Define bridge and explain the type of bridges.
> Bridges
> Types of bridges
Simple bridge
Multiport bridge
Transparent bridge
> Subnetting
> Three levels of hierarchy
> Masking
Masks without subnetting
Masks with subnetting
> Finding the subnetwork address
Boundary level masking
Non-boundary level masking
UNIT IV Transport layer 1. Explain the duties of transport layer.
End to end delivery Addressing Reliable delivery
Error control
Sequence control
Loss control
Duplication control Flow control Multiplexing
Introduction
Explanation
program
> User Datagram Protocol(UDP)
Source port address
Destination port address
Total length
Checksum
> Transmission Control Protocol(TCP)
Source port address
Destination port address
Sequence number
Acknowledgement number
Header length
Reserved
Control
Window size
Check sum
Urgent pointer
Options and padding
4. Explain about congestion control.
> Congestion avoidance
BECN
FECN
Four situations
> Discarding
5. Explain leaky bucket and token bucket algorithm
> Leaky bucket algorithm
Leaky bucket
Switch controlling the output rate
Flowchart
UNIT V Application Layer 1. Explain the functions of SMTP.
System for sending messages to other computer users based on e-mail addresses. SMTP provides mail exchange between users on the same or different computers.
User Agent
Mail Transfer Agent
Multipurpose Internet Mail Extensions
Post Office Protocol
Transfer a file from one system to another.
TCP connections
Basic model of FTP
HTTP transactions
HTTP messages
URL
Hypertext & Hypermedia
Browser Architecture
Categories of Web Documents
HTML
CGI
Java
5. Explain the type of encryption/decryption method.
Conventional Methods:
Character-Level Encryption: Substitutional & Transpositional
Bit-Level Encryption: Encoding/Decoding, Permutation, Substitution, Product, Exclusive-Or & Rotation
Public key Methods
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DEPARTMENT OF COMPUTER SCIENCE AND ENGINEEING
TWO MARK QUESTIONS WITH ANSWERS (For ALL units) SUBJECT NAME : DIGITAL SYSTEMS SUBJECT CODE : CS1202 CLASS : S3 (B.E) CSE
1.Define the term digital.
The term digital refers to any process that is accomplished using discrete
units
2.What is meant by bit?
A binary digit is called bit
3.What is the best example of digital system?
Digital computer is the best example of a digital system.
4.Define byte?
A group of 8 bits.
5.List the number systems?
i) Decimal Number system
ii) Binary Number system
iii) Octal Number system
iv) Hexadecimal Number system
6.State the sequence of operator precedence in Boolean expression?
i) Parenthesis
ii) AND
iii) OR
7.What is the abbreviation of ASCII and EBCDIC code?
ASCII-American Standard Code for Information Interchange. EBCDIC-Extended Binary Coded Decimal Information Code.
8.What are the universal gates?
NAND and NOR
9.What are the different types of number complements?
i) r s Complement
ii) (r-1) s Complement.
10.Why complementing a number representation is needed?
Complementing a number becomes as in digital computer for simplifying the subtraction operation and for logical manipulation complements are used.
11.How to represent a positive and negative sign in computers?
Positive (+) sign by 0
Negative (-) sign by 1.
12.What is meant by Map method?
The map method provides a simple straightforward procedure for minimizing Boolean function.
13.What is meant by two variable map?
Two variable map have four minterms for two variables, hence the map consists of four squares, one for each minterm
14.What is meant by three variable map?
Three variable map have 8 minterms for three variables, hence the map consists of 8 squares, one for each minterm
15.Which gate is equal to AND-inverter Gate?
NAND gate.
16.Which gate is equal to OR-inverter Gate?
NOR gate.
17.Bubbled OR gate is equal to..............
NAND gate
18. Bubbled AND gate is equal to--------------
NOR gate
19.What is the use of Dont care conditions?
Any digital circuit using this code operates under the assumption that these unused combinations will never occur as long as the system
20.Express the function f(x, y, z)=1 in the sum of minterms and a product of maxterms?
Minterms=(0,1,2,3,4,5,6,7)
Maxterms=Nomaxterms.
21.What is the algebraic function of Exclusive-OR gate and Exclusive-NOR gate? F=xy1 + x1y
F=xy +x1y1
22.What are the methods adopted to reduce Boolean function?
i) Karnaugh map
ii) Tabular method or Quine mccluskey method
iii) Variable entered map technique.
23.Why we go in for tabulation method?
This method can be applied to problems with many variables and has the advantage of being suitable for machine computation.
24.State the limitations of karnaugh map.
i) Generally it is limited to six variable map (i.e.) more then six variable involving expressions are not reduced.
ii) The map method is restricted in its capability since they are useful for simplifying only Boolean expression represented in standard form.
25.What is tabulation method?
A method involving an exhaustive tabular search method for the minimum expression to solve a Boolean equation is called as a tabulation method.
26.What are prime-implicants?
The terms remained unchecked are called prime-implecants. They cannot be reduced further.
27.Explain or list out the advantages and disadvantages of K-map method?
The advantages of the K-map method are
i. It is a fast method for simplifying expression up to four variables.
ii. It gives a visual method of logic simplification.
iii. Prime implicants and essential prime implicants are identified fast.
iv. Suitable for both SOP and POS forms of reduction.
v. It is more suitable for class room teachings on logic simplification.
The disadvantages of the K-map method are
i. It is not suitable for computer reduction.
ii. K-maps are not suitable when the number of variables involved exceed four.
iii. Care must be taken to fill in every cell with the relevant entry, such as a 0, 1 (or) dont care terms.
28.List out the advantages and disadvantages of Quine-Mc Cluskey method?
The advantages are,
a. This is suitable when the number of variables exceed four.
b. Digital computers can be used to obtain the solution fast.
c. Essential prime implicants, which are not evident in K-map, can be clearly seen in the final results.
The disadvantages are,
a. Lengthy procedure than K-map.
b. Requires several grouping and steps as compared to K-map.
c. It is much slower.
d. No visual identification of reduction process.
e. The Quine Mc Cluskey method is essentially a computer reduction method.
29.Define Positive Logic.
When high voltage or more positive voltage level is associated with binary 1 and while the low or less positive level is associated with binary 0 then the system adhering to this is called positive logic.
30.Define Negative Logic.
When high voltage level is associated with binary 0 and while the low level is associated with binary 1 then the system adhering to this is called negative logic
31.List the characteristics of digital Ics
i) propagation delay
ii) power dissipation
iii) Fan-in
iv) Fan-out
v) Noise margin
32.What is propagation delay?
It is the average transition delay time for the signal to propagate from input to output when the signals change in value.
33.What is Noise margin?
It is the limit of a noise voltage, which may be present with out impairing the proper operation of the circuit.
34.What is power dissipation?
It is the power consumed by the gate, which must be available from the power supply.
35.Why parity checker is needed?
Parity checker is required at the receiver side to check whether the expected parity is equal to the calculated parity or not. If they are not equal then it is found that the received data has error.
36.What is meant by parity bit?
Parity bit is an extra bit included with a binary message to make the number of 1s either odd or even. The message, including the parity bit is transmitted and then checked at the receiving and for errors.
37.Why parity generator necessary?
Parity generator is essential to generate parity bit in the transmitter.
38.What is IC?
An integrated circuit is a small silicon semiconductor crystal called a chip containing electrical components such as transistors, diodes, resistors and capacitors. The various components are interconnected inside the chip to form an electronic circuit.
39.What are the needs for binary codes?
a. Code is used to represent letters, numbers and punctuation marks.
b. Coding is required for maximum efficiency in single transmission.
c. Binary codes are the major components in the synthesis (artificial generation) of speech and video signals.
d. By using error detecting codes, errors generated in signal transmission can be detected.
e. Codes are used for data compression by which large amounts of data are transmitted in very short duration of time.
40.Mention the different type of binary codes?
The various types of binary codes are,
f. BCD code (Binary Coded decimal).
g. Self-complementing code.
h. The excess-3 (Xs-3) code.
i. Gray code.
j. Binary weighted code. k. Alphanumeric code. l. The ASCII code.
m. Extended binary-coded decimal interchange code (EBCDIC).
n. Error-detecting and error-correcting code.
o. Hamming code.
41.List the advantages and disadvantages of BCD code?
The advantages of BCD code are
a. Any large decimal number can be easily converted into corresponding binary number
b. A person needs to remember only the binary equivalents of decimal number from 0 to 9.
c. Conversion from BCD into decimal is also very easy.
The disadvantages of BCD code are
a. The code is least efficient. It requires several symbols to represent even small numbers.
b. Binary addition and subtraction can lead to wrong answer.
c. Special codes are required for arithmetic operations.
d. This is not a self-complementing code.
e. Conversion into other coding schemes requires special methods.
42.What is meant by self-complementing code?
A self-complementing code is the one in which the members of the number system complement on themselves. This requires the following two conditions to be satisfied.
a. The complement of the number should be obtained from that number by replacing 1s with 0s and 0s with 1s.
b. The sum of the number and its complement should be equal to decimal 9. Example of a self-complementing code is
i. 2-4-2-1 code.
ii. Excess-3 code.
43.Mention the advantages of ASCII code?
The following are the advantages of ASCII code
a. There are 27 =128 possible combinations. Hence, a large number of symbols, alphabets etc.. , can be easily represented.
b. There is a definite order in which the alphabets, etc.. , are assigned to each code word.
c. The parity bits can be added for error-detection and correction.
44.What are the disadvantages of ASCII code?
The disadvantages of ASCII code are
a. The length of the code is larger and hence more bandwidth is required for transmission.
b. With more characters and symbols to represent, this is not completely sufficient.
45.What is the truth table?
A truth table lists all possible combinations of inputs and the corresponding outputs.
46.Define figure of merit?
Figure of merits is defined as the product of speed and power. The speed is specified in terms of propagation delay time expressed in nano seconds.
Figure of merits=Propagation delay time (ns)*
Power (mw)
It is specified in pico joules (ns*mw=PJ).
47.What are the two types of logic circuits for digital systems?
Combinational and sequential
48.Define Combinational circuit.
A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination of inputs without regard to previous inputs.
49.Define sequential circuits.
Their outputs are a function of the inputs and the state of memory elements. The state of memory elements, in turn, is a function of previous inputs.
50.What is a half-adder?
The combinational circuit that performs the addition of two bits are called a half-adder.
51.What is a full-adder?
The combinational circuit that performs the addition of three bits are called a half-adder.
52.What is half-subtractor?
The combinational circuit that performs the subtraction of two bits are called a half-sub tractor.
53.What is a full-subtractor?
The combinational circuit that performs the subtraction of three bits are called a half- sub tractor.
54.What is Binary parallel adder?
A binary parallel adder is a digital function that produces the arithemetic sum of two binary numbers in parallel.
55.What is BCD adder?
A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD.
56.What is Magnitude Comparator?
A Magnitude Comparator is a combinational circuit that compares two numbers, A and B and determines their relative magnitudes.
57.What is decoder?
A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.
58.What is encoder?
A decoder is a combinational circuit that converts binary information from 2nInput lines to a maximum of n unique output lines.
59.Define Multiplexing?
Multiplexing means transmitting a large number of information units over a smaller number of channels or lines.
60.What is Demultiplexer?
A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines
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61.Give the truth table for a half adder. | ||||||||||||||||||||||
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62.Give the truth table for a half Subtractor. | ||||||||||||||||||||||
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63.From the truth table of a half adder derive the logic equation S = X Y
C = X . Y
64. From the truth table of a half subractor derive the logic equation
D = X Y B = X1 . Y
65.From the truth table of a full adder derive the logic equation
S = X Y Z
C = XY + YZ + XZ
66.What is code conversion?
If two systems working with different binary codes are to be synchronized in operation, then we need digital circuit which converts one system of codes to the other. The process of conversion is referred to as code conversion.
67.What is code converter?
It is a circuit that makes the two systems compatible even though each uses a different binary code. It is a device that converts binary signals from a source code to its output code. One example is a BCD to Xs3 converter.
68.What do you mean by analyzing a combinational circuit?
The reverse process for implementing a Boolean expression is called as analyzing a combinational circuit. (ie) the available logic diagram is analyzed step by step and finding the Boolean function
69.Give the applications of Demultiplexer.
i) It finds its application in Data transmission system with error detection.
ii) One simple application is binary to Decimal decoder.
70.Mention the uses of Demultiplexer.
Demultiplexer is used in computers when a same message has to be sent to different receivers. Not only in computers, but any time information from one source can be fed to several places.
71.Give other name for Multiplexer and Demultiplexer.
Multiplexer is other wise called as Data selector.
Demultiplexer is otherwise called as Data distributor.
72.What is the function of the enable input in a Multiplexer?
The function of the enable input in a MUX is to control the operation of the
unit.
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73.Give the truth table for a full Subtractor. | ||||||||||||||||||||||||||||||||||||||||||||||||
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74.Give the truth table for a full adder. | ||||||||||||||||||||||||||||||||||||||||||||||||
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75.From the truth table of a full subtractor derive the logic equation
S = X Y Z C = X1Y + YZ + X1Z
76.What is priority encoder?
A priority encoder is an encoder that includes the priority function. The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.
77.Can a decoder function as a Demultiplexer?
Yes. A decoder with enable can function as a Demultiplexer if the enable line E is taken as a data input line A and B are taken as selection lines.
78.List out the applications of multiplexer?
The various applications of multiplexer are
a. Data routing.
b. Logic function generator.
c. Control sequencer.
d. Parallel-to-serial converter.
79.List out the applications of decoder?
The applications of decoder are
a. Decoders are used in counter system.
b. They are used in analog to digital converter.
c. Decoder outputs can be used to drive a display system.
80.List out the applications of comparators?
The following are the applications of comparator
a. Comparators are used as a part of the address decoding circuitry in computers to select a specific input/output device for the storage of data.
b. They are used to actuate circuitry to drive the physical variable towards the reference value.
c. They are used in control applications.
81.What are the applications of seven segment displays?
The seven segment displays are used in
a. LED displays
b. LCD displays
82.What is digital comparator?
A comparator is a special combinational circuit designed primarily to compare the relative magnitude of two binary numbers.
INPUTS A B
A>B A=B A<B OUTPUTS Block diagram of n-bit comparator
83. List the types of ROM.
i) Programmable ROM (PROM)
ii) Erasable ROM (EPROM)
iii) Electrically Erasable ROM (EEROM)
84.Differentiate ROM & PLDs
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ROM (Read Only Memory) |
PLDs (Programmable Logic Array) |
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1.It is a device that includes both the decoder and the OR gates with in a single IC package |
l.It is a device that includes both AND and OR gates with in a single IC package |
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2.ROM does not full decoding of the variables and does generate all the minterms |
2.PLDs does not provide full decoding of the variable and does not generate all the minterms |
85.What are the different types of RAM?
The different types of RAM are
a. NMOS RAM (Nitride Metal Oxide Semiconductor RAM)
b. CMOS RAM (Complementary Metal Oxide Semiconductor RAM)
c. Schottky TTL RAM
d. ELL RAM.
86.What are the types of arrays in RAM?
RAM has two type of array namely,
a. Linear array
b. Coincident array
87.Explain DRAM?
The dynamic RAM (DRAM) is an operating mod, which stores the binary information in the form of electric charges on capacitors.
The capacitors are provided inside the chip by MOS transistors.
Column (sense line)
Row
(control
line)
Storage
capacitor
DRAM cell
The stored charges on the capacitors tend to discharge with time and the capacitors must be tending to discharge with time and the capacitors must be periodically recharged by refreshing the dynamic memory.
DRAM offers reduced power consumption and larger storage capacity in a single memory chip.
88.Explain SRAM?
Static RAM (SRAM) consists of internal latches that store the binary information. The stored information remains valid as long as the power is applied to the unit.
SRAM is easier to use and has shorter read and write cycle.
The memory capacity of a static RAM varies from 64 bit to 1 mega bit.
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89.Differentiate volatile and non-volatile memory? | ||||
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90.What are the terms that determine the size of a PAL?
The size of a PLA is specified by the
a. Number of inputs
b. Number of products terms
c. Number of outputs
91.What are the advantages of RAM?
The advantages of RAM are
a. Non-destructive read out
b. Fast operating speed
c. Low power dissipation
d. Compatibility
e. Economy
92.What is VHDL?
VHDL is a hardware description language that can be used to model a digital system at many level of abstraction, ranging from the algorithmic level to the gate level.
The VHDL language as a combination of the following language.
a. Sequential language
b. Concurrent language
c. Net-list language
d. Timing specification
e. Waveform generation language.
93.What are the features of VHDL?
The features of VHDL are
a. VHDL has powerful constructs.
b. VHDL supports design library.
c. The language is not case sensitive.
94.Define entity?
Entity gives the specification of input/output signals to external circuitry. An entity is modeled using an entity declaration and at least one architecture body. Entity gives interfacing between device and others peripherals.
95.List out the different elements of entity declaration?
The different elements of entity declaration are:
1. entity_name
2. signal_name
3. mode
4. in:
5. out:
6. input
7. buffer
8. signal_type
96.Give the syntax of entity declaration?
ENTITY entity_name is
PORT (signal_name: mode signal_type;
signal_names: mode signal_type;
signal_names: mode signal_type;
END entity_name;
97.What do you meant by concurrent statement?
Architecture contains only concurrent statements. It specifies behavior, functionality, interconnections or relationship between inputs and outputs.
98.What are operates used in VDHL language?
There are different types of operators used in VHDL language Logical operators : AND, OR, NOT, XOR, etc.,
Relational operator : equal to, <less than etc.,
Shift operators : SLL- Shift Left Logical,
ROR- Rotate Right Logical etc.,
Arithmetic operators: Addition, subtraction etc.,
Miscellaneous operators: <= assign to etc.,
99.Define VHDL package?
A VHDL, package is a file containing definitions of objects which can be used in other programs. A package may include objects such as signals, type, constant, function, procedure and component declarations
100.What is meant by memory decoding?
The memory IC used in a digital system is selected or enabled only for the range of addresses assigned to it .
101.What is access and cycle time?
The access time of the memory is the time to select word and read it. The cycle time of a memory is a time required to complete a write operation.
102.What is sequential circuit?
Sequential circuit is a broad category of digital circuit whose logic states depend on a specified time sequence. A sequential circuit consists of a combinational circuit to which memory elements are connected to form a feedback path.
103.List the classifications of sequential circuit.
i) Synchronous sequential circuit.
ii) Asynchronous sequential circuit.
104.what is Synchronous sequential circuit?
A Synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signal at discrete instants of time.
105.What is clocked sequential circuits?
Synchronous sequential circuit that use clock pulses in the inputs of memory elements are called clocked sequential circuit. One advantage as that they dont cause instability problems.
106.What is called latch?
Latch is a simple memory element, which consists of a pair of logic gates with their inputs and outputs inter connected in a feedback arrangement, which permits a single bit to be stored.
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107.List different types of flip-flops. | ||||||||||||
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108.What do you mean by triggering of flip-flop.
The state of a flip-flop is switched by a momentary change in the input signal. This momentary change is called a trigger and the transition it causes is said to trigger the flip-flop
109.What is an excitation table?
During the design process we usually know the transition from present state to next state and wish to find the flip-flop input conditions that will cause the required transition. A table which lists the required inputs for a given chance of state is called an excitation table.
110.Give the excitation table of a JK flip-flop
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Q(t) |
Q(t+1) |
J |
K |
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0 |
0 |
0 |
X |
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0 |
1 |
1 |
X |
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1 |
0 |
X |
1 |
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1 |
1 |
X |
0 |
111.Give the excitation table of a SR flip-flop
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Q(t) |
Q(t+1) |
S |
R |
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0 |
0 |
0 |
X |
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0 |
1 |
1 |
0 |
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1 |
0 |
0 |
1 |
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1 |
1 |
X |
0 |
112.Give the excitation table of a T flip-flop
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Q(t) |
Q(t+1) |
T |
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0 |
0 |
0 |
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0 |
1 |
1 |
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1 |
0 |
1 |
|
1 |
1 |
0 |
113.Give the excitation table of a D flip-flop
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Q(t) |
Q(t+1) |
T |
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0 |
0 |
0 |
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0 |
1 |
1 |
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1 |
0 |
0 |
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1 |
1 |
1 |
114.What is a characteristic table?
A characteristic table defines the logical property of the flip-flop and completely characteristic its operation.
115.Give the characteristic equation of a SR flip-flop.
Q(t+1)=S+R1Q
116.Give the characteristic equation of a D flip-flop.
Q(t+1)=D
117.Give the characteristic equation of a JK flip-flop.
Q(t+1)=JQ1+K1Q
118.Give the characteristic equation of a T flip-flop.
Q(t+1)=TQ1+T1Q
119.What is the difference between truth table and excitation table.
i) An excitation table is a table that lists the required inputs for a given change of state.
ii) A truth table is a table indicating the output of a logic circuit for various input states.
120.What is counter?
A counter is used to count pulse and give the output in binary form.
121.What is synchronous counter?
In a synchronous counter, the clock pulse is applied simultaneously to all flip-flops. The output of the flip-flops change state at the same instant. The speed of operation is high compared to an asynchronous counter
122.What is Asynchronous counter?
In a Asynchronous counter, the clock pulse is applied to the first flip-flops. The change of state in the output of this flip-flop serves as a clock pulse to the next flip-flop and so on. Here all the flip-flops do not change state at the same instant and hence speed is less.
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123.What is the difference between synchronous and asynchronous counter? | |||||||||
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124.Name the different types of counter.
a) Synchronous counter
b) Asynchronous counter
i) Up counter
ii) Down counter
iii) Modulo - N counter
iv) Up/Down counter
125.What is up counter?
A counter that increments the output by one binary number each time a clock pulse is applied.
126.What is down counter?
A counter that decrements the output by one binary number each time a clock pulse is applied.
127.What is up/down counter?
A counter, which is capable of operating as an up counter or down counter, depending on a control lead.
128.What is a ripple counter?
A ripple counter is nothing but an asynchronous counter, in which the output of the flip-flop change state like a ripple in water.
129.What are the uses of a counter?
i) The digital clock
ii) Auto parking control
iii) Parallel to serial data conversion.
130.What is meant by modulus of a counter?
By the term modulus of a counter we say it is the number of states through which a counter can progress.
131.what is meant by natural count of a counter?
By the term natural count of a counter we say that the maximum number of states through which a counter can progress.
132.A ripple counter is a............sequential counter.
Ans: Synchronous.
133.What is a modulo counter?
A counter that counts from 0 to T is called as modulo counter.
134.A counter that counts from to T is called a modulo counter. True or False. Ans: True
135.The number of flip-flops required for modulo-18 counter is.......
Ans: five.
136.Form the truth table for 3-bit binary down counter.
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Clk |
Q2 |
Q1 |
Q0 |
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1 |
1 |
1 |
1 |
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1 |
1 |
1 |
0 |
|
1 |
1 |
0 |
1 |
|
1 |
1 |
0 |
0 |
|
1 |
0 |
1 |
1 |
|
1 |
0 |
1 |
0 |
|
1 |
0 |
0 |
1 |
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1 |
0 |
0 |
0 |
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1 |
1 |
1 |
1 |
137.What is a ring counter?
A counter formed by circulating a bit in a shift register whose serial output has been connected to its serial input.
138.What is BCD counter?
A BCD counter counts in binary coded decimal from 0000 to 1001 and back to 0000. Because of the return to 0000 after a count of 1001, a BCD counter does not have a regular pattern as in a straight binary counter.
139. What are the uses of a ring counter?
i) Control section of a digital system.
ii) Controlling events, which occur in strict time sequence.
140.What is a register?
Memory elements capable of storing one binary word. It consists of a group of flip-flops, which store the binary information.
141.What is Johnson counter?
It is a ring counter in which the inverted output is fed into the input. It is also know as a twisted ring counter.
142. What is a shift register?
In digital circuits, datas are needed to be moved into a register (shift in) or moved out of a register (shift out). A group of flip-flops having either or both of these facilities is called a shift register.
143. What is serial shifting?
In a shift register, if the data is moved 1 bit at a time in a serial fashion, then the technique is called serial shifting.
144. What is parallel shifting?
In a shift register all the data are moved simultaneously and then the technique is called parallel shifting.
145. Write the uses of a shift register.
i) Temporary data storage
ii) Bit manipulations.
146. What is a cycle counter?
A cycle counter is a counter that outputs a stated number of counts and then
stops.
147. Define state of sequential circuit?
The binary information stored in the memory elements at any given time defines the state of sequential circuits.
148. Define state diagram.
A graphical representation of a state table is called a state diagram.
149. What is the use of state diagram?
i) Behavior of a state machine can be analyzed rapidly.
ii) It can be used to design a machine from a set of specification.
150. What is state table?
A table, which consists time sequence of inputs, outputs and flip-flop states, is called state table. Generally it consists of three section present state, next state and output.
151. What is a state equation?
A state equation also called, as an application equation is an algebraic expression that specifies the condition for a flip-flop state transition. The left side of the equation denotes the next state of the flip-flop and the right side; a Boolean function specifies the present state.
152.What is meant by race around condition?
In JK flip-flop output is fed back to the input, and therefore changes in the output results change in the input. Due to this in the positive half of the clock pulse if J and K are both high then output toggles continuously. This condition is known as race around condition.
153. How many bits would be required for the product register if the multiplier has
6 bits and the multiplicand has 8 bits?
The product register is 14-bit width with extra bit at the left end indicating a temporary storage for any carry, which is generated when the multiplicand is added to the accumulator.
154. What is SM chart?
Just as flow charts are useful in software design, flow charts are useful in the hardware design of digital systems. These flow charts are called as State Machine Flow Charts or SM charts. SM charts are also called as ASMC (Algorithmic State machine chart). ASM chart describes the sequential operation in a digital system.
155. What are the three principal components of SM charts?
The 3 principal components of SM charts are state box, decision box & Conditional output box.
156. What is decision box?
A diamond shaped symbol with true or false branches represents a decision box. The condition placed in the box is a Boolean expression that is evaluated to determine which branch to take in SM chart.
157. What is link path? How many entrance paths & exit paths are there in SM block?
A path through an SM block from entrance to exit is referred to as link path. An SM block has one entrance and exit path.
158. Differentiate ASM chart and conventional flow chart?
A conventional Flow chart describes the sequence of procedural steps and decision paths for an algorithm without concern for their time relationship.
The ASM chart describes the sequence of events as well as the timing relationships between the states of a sequential controller and the events that occur while going from one state to the next.
159. What is flow table?
During the design of synchronous sequential circuits, it is more convenient to name the states by letter symbols without making specific reference to their binary values. Such table is called Flow table.
160. What is primitive flow table?
A flow table is called Primitive flow table because it has only one stable state in each row.
161. Define race condition.
A race condition is said to exist in a synchronous sequential circuit when two or more binary state variables change, the race is called non-critical race.
162. Define critical & non-critical race with example.
The final stable state that the circuit reaches does not depend on the order in which the state variables change, the race is called non-critical race.
The final stable state that the circuit reaches depends on the order in which the state variables change, the race is called critical race.
163. How can a race be avoided?
Races can be avoided by directing the circuit through intermediate unstable states with a unique state - variable change.
164. Define cycle and merging?
When a circuit goes through a unique sequence of unstable states, it is said to have a cyc/e.
The grouping of stab/e states from separate rows into one common row is called merging.
165. Give state - reduction procedure.
The state - reduction procedure for completely specified state tables is baserf on the algorithm that two states in a state table can be combined in to one if they can be shown to be equivalent.
166. Define hazards.
Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delays.
167. Does Hazard occur in sequential circuit? If so what is the problem caused?
Yes, Hazards occur in sequential circuit that is Asynchronous sequential circuit. It may result in a transition to a wrong state.
168. Give the procedural steps for determining the compatibles used for the purpose of merging a flow table.
The purpose that must be applied in order to find a suitable group of compatibles for the purpose of merging a flow table can be divided into 3 procedural steps.
i. Determine all compatible pairs by using the implication table.
ii. Find the maximal compatibles using a Merger diagram
iii. Find a minimal collection of compatibles that covers all the states and is closed.
169. What are the types of hazards?
The 3 types of hazards are 1) Static - 0 hazards
2) Static - 1 hazard
3) Dynamic hazards
170.What is mealy and Moore circuit?
Mealy circuit is a network where the output is a function of both present state and input.
Moore circuit is a network where the output is function of only present state.
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171.Differentiate Moore circuit and Mealy circuit? | ||||
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172. How can the hazards in combinational circuit be removed?
Hazards in the combinational circuits can be removed by covering any two min terms that may produce a hazard with a product term common to both. The removal of hazards requires the addition of redundant gates to the circuit.
173. How does an essential hazard occur?
An essential hazard occurs due to unequal delays along two or more paths that originate from the same input. An excessive delay through an inverter circuit in comparison to the delay associated with the feedback path causes essential hazard.
174.what is Timing diagram?
Timing diagrams are frequently used in the analysis of sequential network.
These diagrams show various signals in the network as a function of time.
175.What is setup and hold time?
The definite time in which the input must be maintained at a constant value prior to the application of the pulse is setup time
The definite time is which the input must not chance after the application of the positive or negative going transition of the pulse based on the triggering of the pulse.
176.Define bit time and word time.
The time interval between clock pulses is called bit time.
The time required to shift the entire contents of a shift register is called word
time.
177.What is bi-directional shift register and unidirectional shift register?
A register capable of shifting both right and left is called bi-directional shift register.
A register capable of shifting only one direction is called unidirectional shift register.
178.Define equivalent state.
If a state machine is started from either of two states and identical output sequences are generated from every possible set of sequences, then the two states are said to be equivalent.
179.If a shift register can be operated in all possible ways then it is called as...........
Ans: Univerasal register: It can be operated in all possible modes with bidirectional shift facility.
180.What is gate delay?
If the change in output is delayed by a time with respect to the input. We say that the gate has a propagation delay of . Normally propagation delay for 0 to 1 output (1) may be different than the delay for 1 to 0 changes (2).
181.Define state reduction algorithm.
State reduction algorithm is stated as Two states are said to be equivalent if, for each member of the set of inputs they give the same output and send the circuit either to the same state or to an equivalent state. When two states are equivalent, one of them can be removed without altering the input-output relation.
182.What is meant by level triggering?
In level triggering the output of the flip-flop changes state or responds only when the clock pulse is present.
183.Write the uses of a shift register.
i) Temporary data storage.
ii) Bit manipulations.
184. What is meant by flow table?
During the design of asynchronous sequential circuits, it is more convenient to name the states by letter symbols without making specific reference to their binary values. Such a table is called a flow table.
185. What are the problems involved in asynchronous circuits?
The asynchronous sequential circuits have three problems namely,
a. Cycles
b. Races
c. Hazards
186. Define cycles?
If an input change includes a feedback transition through more than unstable state then such a situation is called a cycle.
187. Define primitive flow table?
A primitive flow table is a flow table with only one stable total state in each row. Remember that a total state consists of the internal state combined with the input.
188. Define merging?
The primitive flow table has only one stable state in each row. The table can be reduced to a smaller numbers of rows if two or more stable states are placed in the same row of the flow table. The grouping of stable states from separate rows into one common row is called merging.
1. Simplify the following Boolean function by using Tabulation method
F (w, x, y, z) =(0,1,2,8,10,11,14,15)
Determination of Prime Implicants
Selection of prime Implicants
2. Simplify the following Boolean functions by using KMap in SOP & POS.
F (w, x, y, z) =(1,3,4,6,9,11,12,14)
Find the Number of variable map
Draw the Map
Simplification of SOP & POS
3. Simplify the following Boolean functions by using KMap in SOP & POS.
F (w, x, y, z) =(1,3,7,11,15) + d(0,2,5)
Find the Number of variable map
Dont care treat as variable X.
Draw the Map
Simplification of SOP & POS
4. Reduce the given expression.
[(AB) !+ A 1 +AB] 1
Reduce the expression using Boolean algebra Laws and theorems
5. Reduce the given function minimum number of literals.
(abc) !+ a Vac
Reduce the expression using Boolean algebra Laws and theorems
1. Design a combinational logic circuit to convert the Gray code into Binary code
Truth table
KMap Simplification
Draw the Logic Diagram
2. Draw the truth table and logic diagram for full-Adder
Truth table
KMap Simplification
Draw the Logic Diagram
3. Draw the truth table and logic diagram for full-Subtractor
Truth table
KMap Simplification
Draw the Logic Diagram
4. Explain Binary parallel adder.
Explanation
Logic diagram
5. Design a combinational logic circuit to convert the BCD to Binary code
Truth table
KMap Simplification
Draw the Logic Diagram
1. Implement the following function using PLA.
A (x, y, z) = Em (1, 2, 4, 6)
B (x, y, z) = Em (0, 1, 6, 7)
C (x, y, z) = Em (2, 6)
KMap Simplification
PLA table
PLA Logic Diagram
2. Implement the following function using PAL.
W (A, B, C, D) = Em (2, 12, 13)
X (A, B, C, D) = Em (7, 8, 9, 10, 11, 12, 13, 14, 15)
Y (A, B, C, D) = Em (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) Z (A, B, C, D) = Em (1, 2, 8, 12, 13)
KMap Simplification
PAL Logic diagram
3.Implement the given function using multiplexer
Implementation table
Multiplexer Implementation
4. Explain about Encoder and Decoder?
Definition
Truth table
Logic Diagram
5. Explain about 4 bit Magnitude comparator?
Explanation
Logic Diagram
UNIT IV
1. Design a counter with the following repeated binary sequence:0, 1, 2, 3, 4, 5, 6. use JK Flip-flop.
State diagram
Excitation State table
KMap Simplification
Logic diagram
2. Describe the operation of SR flip-flop
Logic Diagram
Graphical Symbol
Characteristics table
Characteristics equation
Excitation Table
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3. Design a sequential circuit using JK flip-flop for the following state table [use state diagram]_ | ||||||||||||||||||||||||||||||
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State Diagram
Excitation state table
KMap simplification
Logic Diagram
4. The count has a repeated sequence of six states, with flip flops B and C repeating the binary count 00, 01, 10 while flip flop A alternates between 0 and 1 every three counts. Designs with JK flip-flop
State diagram
Excitation State table
KMap Simplification
Logic diagram
5. Design a 3-bit T flip-flop counter
State diagram
Excitation State table
KMap Simplification
Logic diagram
1. Design an Asynchronous sequential circuit using SR latch with two inputs A and B and one output y. B is the control input which, when equal to 1, transfers the input A to output y. when B is 0, the output does not change, for any change in input.
State Table
Primitive Flow Table
Formal Reduction (Implication Method)
Merging
Reduced Table
KMap Simplification
Logic Diagram
2. Give hazard free relation for the following Boolean function.
F (A, B, C, D) =Em (0, 2, 6, 7, 8, 10, 12)
KMap simplification
Create Hazard free link
3. Explain about Hazards?
Explain Static Hazard
Explain Dynamic Hazard
4. Explain about Races?
Explain Critical Race
Explain Non-Critical Race
5. Design T Flip flop from Asynchronous Sequential circuit?
State Table
Primitive Flow Table
Formal Reduction (Implication Method)
Merging
Reduced Table
KMap Simplification
Logic Diagram
NOORUL ISLAM COLLEGE OF ENGG,
Kumaracoil DEPARTMENT OF ECE
2 MARKS & QUESTION- ANSWERS
EC 1302- Digital Signal Processing Class: S5 ECE (A&B)
Prepared by : G.Sofia, Lecturer/ECE
Digital Signal Processing S5ECE A&B
1. What is a continuous and discrete time signal?
Ans:
Continuous time signal: A signal x(t) is said to be continuous if it is defined for all time t. Continuous time signal arise naturally when a physical waveform such as acoustics wave or light wave is converted into a electrical signal. This is effected by means of transducer.(e.g.) microphone, photocell.
Discrete time signal: A discrete time signal is defined only at discrete instants of time. The independent variable has discrete values only, which are uniformly spaced. A discrete time signal is often derived from the continuous time signal by sampling it at a uniform rate.
2. Give the classification of signals?
Ans:
Continuous-time and discrete time signals Even and odd signals Periodic signals and non-periodic signals Deterministic signal and Random signal Energy and Power signal
3. What are the types of systems?
Ans:
Continuous time and discrete time systems
Linear and Non-linear systems
Causal and Non-causal systems
Static and Dynamic systems
Time varying and time in-varying systems
Distributive parameters and Lumped parameters systems
Stable and Un-stable systems.
4. What are even and odd signals?
Ans:
Even signal: continuous time signal x(t) is said to be even if it satisfies the condition x(t)=x(-t) for all values of t.
Odd signal: he signal x(t) is said to be odd if it satisfies the condition x(-t)=-x(t) for all t. In other words even signal is symmetric about the time origin or the vertical axis, but odd signals are anti-symmetric about the vertical axis.
5. What are deterministic and random signals?
Ans:
Deterministic Signal: deterministic signal is a signal about which there is no certainty with respect to its value at any time. Accordingly we find that deterministic signals may be modeled as completely specified functions of time.
Random signal: random signal is a signal about which there is uncertainty before its actual occurrence. Such signal may be viewed as group of signals with each signal in the ensemble having different wave forms
.(e.g.) The noise developed in a television or radio amplifier is an example for random signal.
6. What are energy and power signal?
Ans:
Energy signal: signal is referred as an energy signal, if and only if the total energy of the signal satisfies the condition 0<E<j. The total energy of the continuous time signal x(t) is given as
E=limTJx2 (t)dt, integration limit from -T/2 to +T/2
Power signal: signal is said to be powered signal if it satisfies the condition 0<P< j.
The average power of a continuous time signal is given by P=limTJ1/Tjx2(t)dt, integration limit is from-T/2 to +t/2.
7. What are the operations performed on a signal?
Ans:
Operations performed on dependent variables:
Amplitude scaling: y (t) =cx (t), where c is the scaling factor, x(t) is the continuous time signal.
Addition: y (t)=x1(t)+x2(t)
Multiplication y (t)=x1(t)x2(t)
Differentiation: y (t)=d/dt x(t)
Integration (t) =Jx(t)dt
Operations performed on independent variables Time shifting Amplitude scaling Time reversal
8. What are elementary signals and name them?
Ans:
The elementary signals serve as a building block for the construction of more complex signals. They are also important in their own right, in that they may be used to model many physical signals that occur in nature.
There are five elementary signals. They are as follows
Unit step function Unit impulse function Ramp function Exponential function Sinusoidal function
9. What are the properties of a system?
Ans:
Stability: A system is said to be stable if the input x(t) satisfies the condition(t) | <Mx<ro and the out put satisfies the condition | y(t) | <My<ro for all t.
Memory: A system is said to be memory if the output signal depends on the present and the past inputs.
Invertibility: A system is said to be invertible if the input of the system con be recovered from the system output.
Time invariance: A system is said to be time invariant if a time delay or advance of the input signal leads to an identical time shift in the output signal.
Linearity: A system is said to be linear if it satisfies the super position principle
i.e.) R(ax1(t)+bx2(t))=ax1(t)+bx2(t)
10. What is memory system and memory less system?
Ans:
A system is said to be memory system if its output signal at any time depends on the past values of the input signal. circuit with inductors capacitors are examples of memory system..
A system is said to be memory less system if the output at any time depends on the present values of the input signal. An electronic circuit with resistors is an example for memory less system.
11. What is an invertible system?
Ans:
A system is said to be invertible system if the input of the system can be recovered from the system output. The set of operations needed to recover the input as the second system connected in cascade with the given system such that the output signal of the second system is equal to the input signal applied to the system.
H-1{y(t)}=H-1{H{x(t)}}.
12. What are time invariant systems?
Ans:
A system is said to be time invariant system if a time delay or advance of the input signal leads to an idenditical shift in the output signal. This implies that a time invariant system responds idenditically no matter when the input signal is applied. It also satisfies the condition
R{x(n-k)}=y(n-k).
13. Is a discrete time signal described by the input output relation y[n]= rnx[n] time invariant.
Ans:
A signal is said to be time invariant if R{x[n-k] }= y[n-k]
R{x[n-k] }=R(x[n]) / x[n]x[n-k]
=rnx [n-k]----------------(1)
y[n-k]=y[n] / nn-k
=rn-kx [n-k]-------------------(2)
Equations (1)Equation(2)
Hence the signal is time variant.
14. Show that the discrete time system described by the input-output relationship y[n] =nx[n] is linear?
Ans:
For a sys to be linear R{aixi[n]+bix2[n] }=aiyi[n]+biy2[n]
L.H.S:R{ a1x1[n]+b1x2[n] }=R{x[n]} /x[n] a1x1[n]+b1x2[n]
= ai nxi[n]+bi nx2[n] -------------------(1)
R.H.S: aiyi[n]+biy2[n]= ai nxi[n]+bi nx2[n] --------------------(2)
Equation(i)=Equation(2)
Hence the system is linear
15. What is SISO system and MIMO system?
Ans:
A control system with single input and single output is referred to as single input single output system. When the number of plant inputs or the number of plant outputs is more than one the system is referred to as multiple input output system. In both the case, the controller may be in the form of a digital computer or microprocessor in which we can speak of the digital control systems.
16. What is the output of the system with system function H1 and H2 when connected in cascade and parallel?
Ans:
When the system with input x(t) is connected in cascade with the system Hi and H2 the output of the system is
y(t)=H2{Hi{x(t)}}
When the system is connected in parallel the output of the system is given by
y(t)=HiXi(t)+H2X2(t).
17. What do you mean by periodic and non-periodic signals?
A signal is said to be periodic if x(n+N)=x(n)
Where N is the time period.
A signal is said to be non-periodic if x(n+N)#(n) .
18.Determine the convolution sum of two sequences x(n) = {3, 2,1, 2} and
Ans: y(n) = {3,8,8,12,9,4,4}
19.Find the convolution of the signals
x(n) = 1 n=-2,0,1 = 2 n=-1 = 0 elsewhere.
Ans: y(n) = {1,1,0,1,-2,0,-1}
20.Detemine the solution of the difference equation
y(n) = 5/6 y(n-1) - 1/6 y(n-2) + x(n) for x(n) = 2n u(n)
Ans: y(n) = -(1/2)n u(n) + 2/3(1/3)n u(n)+8/5 2nu(n)
21.Determine the response y(n), n>=0 of the system described by the second order difference equation
y(n) - 4y(n-1) + 4y(n-2) = x(n) - x(n-1) when the input is x(n) = (-1)n u(n) and the initial condition are y(-1) = y(-2)=1.
Ans:y(n) = (7/9-5/3n)2n u(n) +2/9(-1)n u(n)
22. Differentiate DTFT and DFT
DTFT output is continuous in time where as DFT output is Discrete in time.
23.Differentiate between DIT and DIF algorithm
DIT - Time is decimated and input is bi reversed format output in natural order DIF - Frequency is decimated and input is natural order output is bit reversed format.
24. How many stages are there for 8 point DFT
8
25 How many multiplication terms are required for doing DFT by expressional method and FFT method
expression -n2 FFT N /2 log N
26. Distinguish HR and FIR filters
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27. Distinguish analog and digital filters |
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Analog |
digital |
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Constructed using active or passive components and it is described by a differential equation |
Consists of elements like adder, subtractor and delay units and it is described by a difference equation |
|
Frequency response can be changed by changing the components |
Frequency response can be changed by changing the filter coefficients |
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It processes and generates analog output |
Processes and generates digital output |
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Output varies due to external conditions |
Not influenced by external conditions |
28. Write the expression for order of Butterworth filter?
The expression is N=log (k /) 1/2/log (1/k) 1/2
29. Write the expression for the order of chebyshev filter?
N=cosh-1(k /e)/cosh-1(1/k)
30. Write the various frequency transformations in analog domain?
LPF to LPF:s=s/Qc LPF to HPF:s=Qc/s LPF to BPF:s=s2xlxu/s(xu-xl)
LPF to BSF:s=s(xu-xl)?s2=xlxu. X=Q
31. Write the steps in designing chebyshev filter?
1. Find the order of the filter.
2. Find the value of major and minor axis. k
3. Calculate the poles.
4. Find the denominator function using the above poles.
5. The numerator polynomial value depends on the value of n.
If n is odd: put s=0 in the denominator polynomial.
If n is even put s=0 and divide it by (1+e2)1/2
32. Write down the steps for designing a Butterworth filter?
1. From the given specifications find the order of the filter 2 find the transfer function from the value of N
3. Find Qc
4 find the transfer function ha(s) for the above value of Qc by su s by that value.
33. State the equation for finding the poles in chebyshev filter
sk=acos0k+jbsin0k,where 0k=n/2+(2k-1)/2n)n
34. State the steps to design digital IIR filter using bilinear method
Substitute s by 2/T (z-1/z+1), where T=2/Q (tan (w/2) in h(s) to get h (z)
35. What is warping effect?
For smaller values of w there exist linear relationship between w and .but for larger values of w the relationship is nonlinear. This introduces distortion in the frequency axis. This effect compresses the magnitude and phase response. This effect is called warping effect
36. Write a note on pre warping.
The effect of the non linear compression at high frequencies can be compensated. When the desired magnitude response is piecewise constant over frequency, this compression can be compensated by introducing a suitable rescaling or prewar ping the critical frequencies.
37. Give the bilinear transform equation between s plane and zplane
s=2/T (z-1/z+1)
38. Why impulse invariant method is not preferred in the design of IIR filters other than low pass filter?
In this method the mapping from s plane to z plane is many to one. Thus there ire an infinite number of poles that map to the same location in the z plane, producing an aliasing effect. It is inappropriate in designing high pass filters. Therefore this method is not much preferred.
39. By impulse invariant method obtain the digital filter transfer function and the differential equation of the analog filter h(s) =1/s+1
H (z) =1/1-e"V
Y/x(s) =1/s+1
Cross multiplying and taking inverse lap lace we get,
D/dt(y(t)+y(t)=x(t)
40. What is meant by impulse invariant method?
In this method of digitizing an analog filter, the impulse response of the resulting digital filter is a sampled version of the impulse response of the analog filter. For
e.g. if the transfer function is of the form, 1/s-p, then H (z) =1/1-e-pTz-1
41. What do you understand by backward difference?
One of the simplest methods of converting analog to digital filter is to approximate the differential equation by an equivalent difference equation. d/dt(y(t)/t=nT=(y(nT)-y(nT-T))/T
42. What are the properties of chebyshev filter?
1. The magnitude response of the chebyshev filter exhibits ripple either in the stop band or the pass band.
2. The poles of this filter lies on the ellipse
43. Give the Butterworth filter transfer function and its magnitude characteristics for different orders of filter.
The transfer function of the Butterworth filter is given by H (j'Q) =1/1+j (Q/Qc) N
44. Give the magnitude function of Butterworth filter.
The magnitude function of Butterworth filter is lh(jQ)=1/[1+(Q/Qc)2N]1/2 ,N=1,2,3,4,....
45. Give the equation for the order N, major, minor axis of an ellipse in case of chebyshev filter?
The order is given by N=cosh"1(((101ap)-1/101as-1)1/2))/cosh"1'Qs/Qp
a / 1/N -1/N\//f~v
A= ( - )/2Qp
ID / 1/N -1/N\ frs
B=Qp ( + )/2
46. Give the expression for poles and zeroes of a chebyshev type 2 filters
The zeroes of chebyshev type 2 filter SK=j'Qs/sinkOk, k=1..N
The poles of this filter xk+jyk xk= 'Qsok/ 'Qs2+ok2 yk='Qs'Qk/ 'Qs2+ok2 ok=acosOk
47. How can you design a digital filter from analog filter?
Digital filter can de designed from analog filter using the following methods
1. Approximation of derivatives
2. Impulse invariant method
3. Bilinear transformation
48. write down bilinear transformation.
s=2/T (z- 1/z+1)
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49. List the Butterworth polynomial for various orders. | ||||||||||||||||
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50. Differentiate Butterworth and Chebyshev filter.
Butterworth dampimg factor 1.44 chebyshev 1.06 Butterworth flat response damped response.
51. What is filter?
Filter is a frequency selective device ,which amplify particular range of frequencies and attenuate particular range of frequencies.
52. What are the types of digital filter according to their impulse response?
IIR(Infinite impulse response filter FIR(Finite Impulse Response)filter.
53. How phase distortion and delay distortion are introduced?
The phase distortion is introduced when the phase characteristics of a filter is nonlinear with in the desired frequency band.
The delay distortion is introduced when the delay is not constant with in the desired frequency band.
54. what is mean by FIR filter?
The filter designed by selecting finite number of samples of impulse response (h(n) obtained from inverse fourier transform of desired frequency response H(w)) are called FIR filters
55. Write the steps involved in FIR filter design
Choose the desired frequency response Hd(w)
Take the inverse fourier transform and obtain Hd(n)
Convert the infinite duration sequence Hd(n) to h(n)
Take Z transform of h(n) to get H(Z)
56. What are advantages of FIR filter?
Linear phase FIR filter can be easily designed .
Efficient realization of FIR filter exists as both recursive and non-recursive structures.
FIR filter realized non-recursively stable.
The round off noise can be made small in non recursive realization of FIR filter.
57. What are the disadvantages of FIR FILTER
The duration of impulse response should be large to realize sharp cutoff filters. The non integral delay can lead to problems in some signal processing applications.
58. What is the necessary and sufficient condition for the linear phase characteristic of a FIR filter?
The phase function should be a linear function of w, which inturn requires constant group delay and phase delay.
59. List the well known design technique for linear phase FIR filter design?
Fourier series method and window method Frequency sampling method.
Optimal filter design method.
60. Define IIR filter?
The filter designed by considering all the infinite samples of impulse response are called IIR filter.
61. For what kind of application, the antisymmetrical impulse response can be used?
The ant symmetrical impulse response can be used to design Hilbert transforms and differentiators.
62. For what kind of application, the symmetrical impulse response can be used?
The impulse response ,which is symmetric having odd number of samples can be used to design all types of filters ,i.e , lowpass,highpass,bandpass and band reject. The symmetric impulse response having even number of samples can be used to design lowpass and bandpass filter.
63.What is the reason that FIR filter is always stable?
FIR filter is always stable because all its poles are at the origin.
64.What condition on the FIR sequence h(n) are to be imposed n order that this filter can be called a liner phase filter?
The conditions are
(i) Symmetric condition h(n)=h(N-1-n)
(ii) Antisymmetric condition h(n)=-h(N-1-n)
65. Under what conditions a finite duration sequence h(n) will yield constant group delay in its frequency response characteristics and not the phase delay?
If the impulse response is anti symmetrical ,satisfying the condition
H(n)=-h(N-1-n)
The frequency response of FIR filter will have constant group delay and not the phase delay .
66. State the condition for a digital filter to be causal and stable?
A digital filter is causal if its impluse response h(n)=0 for n<0.
A digital filter is stable if its impulse response is absolutely summable ,i.e,
X |h(n)|<
n=-<
67. What are the properties of FIR filter?
1.FIR filter is always stable.
2.A realizable filter can always be obtained.
3.FIR filter has a linear phase response.
68. When cascade from realization is preferred in FIR filters?
The cascade from realization is preferred when complex zeros with absolute magnitude less than one.
69. What are the disadvantage of Fourier series method ?
In designing FIR filter using Fourier series method the infinite duration impulse response is truncated at n= (N-1/2).Direct truncation of the series will lead to fixed percentage overshoots and undershoots before and after an approximated discontinuity in the frequency response .
70. What is Gibbs phenomenon?
OR
What are Gibbs oscillations?
One possible way of finding an FIR filter that approximates H(ejo>)would be to truncate the infinite Fourier series at n= (N-1/2).Abrupt truncation of the series will lead to oscillation both in pass band and is stop band .This phenomenon is known as Gibbs phenomenon.
71. What are the desirable characteristics of the windows?
The desirable charaterstics of the window are
1.The central lobe of the frequency response of the window should contain most of the energy and should be narrow.
2.The highest side lobe level of the frequency response should be small.
3.The sides lobes of the frequency response should decrease in energy rapidly as o> tends to n .
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72. Compare Hamming window with Kaiser window. | ||||
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73.What is the necessary and sufficient condition for linear phase characteristics in FIR filter?
The necessary and sufficient condition for linear phase characteristics in FIR filter is the impulse response h(n) of the system should have the symmetry property,i.e, H(n) = h(N-l-n)
Where N is the duration of the sequence .
74.What are the advantage of Kaiser widow?
l.It provides flexibility for the designer to select the side lobe level and N .
2. It has the attractive property that the side lobe level can be varied continuously from the low value in the Blackman window to the high value in the rectangle window .
75.What is the principle of designing FIR filter using frequency sampling method?
In frequency sampling method the desired magnitude response is sampled and a linear phase response is specified .The samples of desired frequency response are defined as DFT coefficients. The filter coefficients are then determined as the IDFT of this set of samples.
76.For what type of filters frequency sampling method is suitable?
Frequency sampling method is attractive for narrow band frequency selective filters where only a few of the samples of the frequency response are non-zero.
77.What is meant by autocorrelation?
The autocorrelation of a sequence is the correlation of a sequence with its shifted version, and this indicates how fast the signal changes.
78.Define white noise?
A stationary random process is said to be white noise if its power density spectrum is constant. Hence the white noise has flat frequency response spectrum.
2
SX(w) = ox , -n < wn
79.what do you understand by a fixed-point number?
In fixed point arithmetic the position of the binary point is fixed. The bit to the right represent the fractional part of the number & those to the left represent the integer part. For example, the binary number 01.1100 has the value 1.75 in decimal.
80.What is the objective of spectrum estimation?
The main objective of spectrum estimation is the determination of the power spectral density of a random process. The estimated PSD provides information about the structure of the random process which can be used for modeling, prediction or filtering of the deserved process.
81.List out the addressing modes supported by C5Xprocessors?
1. Direct addressing
2. Indirect addressing
3. Immediate addressing
4. Dedicated-register addressing
5. Memory-mapped register addressing
6. Circular addressing
82.what is meant by block floating point representation? What are its advantages?
In block point arithmetic the set of signals to be handled is divided into blocks. Each block have the same value for the exponent. The arithmetic operations with in the block uses fixed point arithmetic & only one exponent per block is stored thus saving memory. This representation of numbers is more suitable in certain FFT flow graph & in digital audio applications.
83.what are the advantages of floating point arithmetic?
1. Large dynamic range
2. Over flow in floating point representation is unlike.
84.what are the three-quantization errors to finite word length registers in digital filters?
1. Input quantization error 2. Coefficient quantization error 3. Product quantization
error
85.How the multiplication & addition are carried out in floating point arithmetic?
In floating point arithmetic, multiplication are carried out as follows,
Let f1 = M1*2c1 and f2 = M2*2c2. Then f3 = f1*f2 = (M1*M2) 2(c1+c2)
That is, mantissa is multiplied using fixed-point arithmetic and the exponents are added.
The sum of two floating-point number is carried out by shifting the bits of the mantissa
of the smaller number to the right until the exponents of the two numbers are equal and then adding the mantissas.
86.What do you understand by input quantization error?
In digital signal processing, the continuous time input signals are converted into digital using a b-bit ACD. The representation of continuous signal amplitude by a fixed digit produce an error, which is known as input quantization error.
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87.List the on-chip peripherals in 5X. The C5X DSP on-chip peripherals available are as follows: | ||||||||||||||||||
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88.what is the relationship between truncation error e and the bits b for representing a decimal into binary?
For a 2's complement representation, the error due to truncation for both positive and negative values of x is 0>=xt-x>-2-b
Where b is the number of bits and xt is the truncated value of x.
The equation holds good for both sign magnitude, 1's complement if x>0
If x<0, then for sign magnitude and for 1's complement the truncation error satisfies.
89.what is meant rounding? Discuss its effect on all types of number representation?
Rounding a number to b bits is accomplished by choosing the rounded result as the b bit number closest to the original number unrounded.
For fixed point arithmetic, the error made by rounding a number to b bits satisfy the inequality
-2-b 2-b
-----<=xt-x<= --------
2 2
for all three types of number systems, i.e., 2's complement, 1's complement & sign magnitude.
For floating point number the error made by rounding a number to b bits satisfy the inequality
-2-b<=E<=2-b where E=xt-x
90.what is meant by A/D conversion noise?
A DSP contains a device, A/D converter that operates on the analog input x(t) to produce xq(t) which is binary sequence of 0s and 1s.
At first the signal x(t) is sampled at regular intervals to produce a sequence x(n) is of infinite precision. Each sample x(n) is expressed in terms of a finite number of bits given the sequence xq(n). The difference signal e(n)=xq(n)-x(n) is called A/D conversion noise.
91.what is the effect of quantization on pole location?
Quantization of coefficients in digital filters lead to slight changes in their value. This change in value of filter coefficients modify the pole-zero locations. Some times the pole locations will be changed in such a way that the system may drive into instability.
92.which realization is less sensitive to the process of quantization?
Cascade form.
93.what is meant by quantization step size?
Let us assume a sinusoidal signal varying between +1 and -1 having a dynamic range
2. If the ADC used to convert the sinusoidal signal employs b+1 bits including sign bit, the number of levels available for quantizing x(n) is 2b+1. Thus the interval between successive levels
q= 2 =2-b
2b+1
Where q is known as quantization step size.
94.How would you relate the steady-state noise power due to quantization and the b bits representing the binary sequence?
Steady state noise power
Where b is the number of bits excluding sign bit.
95.what is overflow oscillation?
The addition of two fixed-point arithmetic numbers cause over flow the sum exceeds the word size available to store the sum. This overflow caused by adder make the filter output to oscillate between maximum amplitude limits. Such limit cycles have been referred to as over flow oscillations.
96.what are the methods used to prevent overflow?
There are two methods used to prevent overflow
1. Saturation arithmetic 2. Scaling
97.what are the two kinds of limit cycle behavior in DSP?
1.zero input limit cycle oscillations 2.Overflow limit cycle oscillations
98.Determine ''dead band of the filter
The limit cycle occur as a result of quantization effect in multiplication. The amplitudes of the output during a limit cycle are confined to a range of values called the dead band of the filter.
99.Explain briefly the need for scaling in the digital filter implementation.
To prevent overflow, the signal level at certain points in the digital filter must be scaled so that no overflow occurs in the adder.
100.What are the different buses of TMS320C5X and their functions?
The C5X architecture has four buses and their functions are as follows: Program bus (PB):
It carries the instruction code and immediate operands from program memory space to the CPU.
Program address bus (PAB):
It provides addresses to program memory space for both reads and writes. Data read bus (DB):
It interconnects various elements of the CPU to data memory space.
Data read address bus (DAB):
It provides the address to access the data memory space.
1. Determine the DFT of the sequence
x(n) =1/4, for 0<=n <=2
0, otherwise
Ans: The N point DFT of the sequence x(n) is defined as N-1
x(k)= X x(n)e-j2nnk/N K=0,1,2,3,...N-1 n=0
x(n) = (1/4,1/4,1/4)
X(k) = / e-j2nk/3[1+2cos(2nk/3)] where k= 0,1,..........,N-1
2. Derive the DFT of the sample data sequence x(n) = {1,1,2,2,3,3}and compute the corresponding amplitude and phase spectrum.
Ans: The N point DFT of the sequence x(n) is defined as N-1
X(k)= X x(n)e-j2nnk/N K=0,1,2,3,...N-1
n=0 X(0) = 12 X(1) = -1.5 + j2.598 X(2) = -1.5 + j0.866 X(3) = 0
X(4) = -1.5 - j0.866 X(5) =-1.5-j2.598
X(k) = {12, -1.5 + j2.598, -1.5 + j0.866,0, -1.5 - j0.866, -1.5-j2.598} IX(k)l={ 12,2.999,1.732,0,1.732,2.999}
LX(k)={0,- n/3,- n/6,0, n/6, n/3}
3.Given x(n) = {0,1,2,3,4,5,6,7} find X(k) using DIT FFT algorithm.
Ans: Given N = 8
WNk = e-j(2n/N)k W80 = 1
W81 =0.707-j0.707 W82 = -j
W83 = -0.707-j0.707 Using butterfly diagram
X(k) = {28,-4+j9.656,-4+j4,-4+j 1.656,-4,-4-j 1.656,-4-j4,-4-j9.656}
4.Given X(k) = {28,-4+j9.656,-4+j4,-4+j 1.656,-4,-4-j 1.656,-4-j4,-4-j9.656} find x(n) using inverse DIT FFT algorithm.
WNk = ej(2n/N)k W80 = 1
W81 =0.707+j0.707 W82 = j
W83 = -0.707+j0.707 x(n) = {0,1,2,3,4,5,6,7}
5.Find the inverse DFT of X(k) = {1,2,3,4}
Ans: The inverse DFT is defined as
N-1
x(n)=(1/N ) X x(k)ej2nnk/N n=0,1,2,3,...N-1
k=0
x(0) = 5/2 x(1) = - 1/2-j 1/2 x(2) =-1/2 x(3) = - 1/2+j 1/2
x(n) = {5/2, - 1/2-j 1/2, -1/2, -1/2+j1/2}
6. Design an ideal low pass filter with a frequency response Hd(e jw) =1 for -
n/2<=w<=n/2
0 otherwise
find the value of h(n) for N=11 find H(Z) plot magnitude response
a. Find h(n) by IDTFT
b. Convert h(n) in to a fine length by truncation
c. H(0)=1/2, h(1)=h(-1)=0.3183 h(2)=h(-2)=0 h(3)=h(-3)= -0.106 h(4)=h(-4)=0 h(5)=h(-5)=0.06366
d' Find the transfer function H(Z) which is not realizable conver in to realizable by multiplying by z"(N"1/2)
e. H(Z) obtained is 0.06366-0.106z2+.3183Z4+.5Z5+.3183Z6-.106Z1+0.06366Z"
10
f. Find H (e jw) and plot amplitude response curve.
7. Design an ideal low pass filter with a frequency response Hd(e jw) =1 for -
n/4<=iwi<=n
0 otherwise
find the value of h(n) for N=11 find H(Z) plot magnitude response
g. Find h(n) by IDTFT
h. Convert h(n) in to a fine length by truncation
i. H(0)=0.75 h(1)=h(-1)=-.22 h(2)=h(-2)=-.159 h(3)=h(-3)= -0.075 h(4)=h(-4)=0 h(5)=h(-5)=0.045
J' Find the transfer function H(Z) which is not realizable conver in to realizable by multiplying by z"(N"1/2) k. H(Z) obtained is 0.045-0.075z-2 -.159 Z-3-0.22Z"4+0.75Z5-.22Z"6 -0.159Z-7 -.
075Z-8+0.045Z-10
l. Find H (e jw) and plot amplitude response curve.
m. Find h(n) by IDTFT
n. Convert h(n) in to a fine length by truncation
o. Find the transfer function H(Z) which is not realizable conver in to realizable by multiplying by z-(N-1/2) p. H(Z) obtained Find H (e jw) and plot amplitude response curve.
9. Design band reject filter with a frequency response Hd(e jw) =1 for n/4<=lwl<=3n/4
0 otherwise
find the value of h(n) for N=11 find H(Z) plot magnitude response q. Find h(n) by IDTFT
r. Convert h(n) in to a fine length by truncation
s. Find the transfer function H(Z) which is not realizable conver in to realizable by multiplying by z-(N-1/2) t. H(Z) obtained Find H (e jw) and plot amplitude response curve.
10. Derive the condition of FIR filter to be linear in phase.
Conditions are
Group delay and Phase delay should be constant And
And show the condition is satisfied
11Derive the expression for steady state I/P Noise Power and Steady state O/P Noise Power.
Write the derivation.
12 Draw the product quantatization model for first order and second order filter Write the difference equation and draw the noise model.
13 For the second order filter Draw the direct form II realization and find the scaling factor S0 to avoid over flow Find the scaling factor from the formula 1+r2
I= ---------------------------------------
(1-r2)(1-2r2cos20 =r4)
14 Explain Briefly about various number representation in digital computer.
1 Fixed point
2 Floating point
3 Block floating point
Signed magnitude represenation 1s Complement 2s Complement etc
15 Consider the transfer function H(Z)=H1(Z)H2(Z) where H1(Z) =1/1-a1Z-1 H2(z) =1/ 1-a2Z-1
Find the o/p Round of noise power Assume a1=0.5 and a2= 0.6 and find o.p round off noise power.
Draw the round of Noise Model.
By using residue method find o01 By using residue method find o 02 = o oi 2+ o 02 2
2 -2b (5.43)
Ans:_
12
16.Explain the architecture of DSP processor .
Diagram. & explanation.
17.Describe briefly the different methods of power spectral estimation?
1. Bartlett method
2. Welch method
3. Blackman-Tukey method and its derivation.
18.what is meant by A/D conversion noise. Explain in detail?
A DSP contains a device, A/D converter that operates on the analog input x(t) to produce xq(t) which is binary sequence of 0s and 1s.
At first the signal x(t) is sampled at regular intervals to produce a sequence x(n) is of infinite precision. Each sample x(n) is expressed in terms of a finite number of bits given the sequence xq(n). The difference signal e(n)=xq(n)-x(n) is called A/D conversion noise.
+ derivation.
19 onsider the transfer function H(Z)=H1(Z)H2(Z) where H1(Z) =1/1-a1Z-1 H2(z) =1/ 1-a2Z-1
Find the o/p Round of noise power Assume a1=0.7 and a2= 0.8and find o.p round
Draw the round of Noise Model.
By using residue method find o01 By using residue method find o 02 = o 01 2+ o 02 2
20.Given X(k) = {1,1,1,1,1,1,1,1,} find x(n) using inverse DIT FFT algorithm.
WNk = ej(2n/N)k
Find x(n)
21.Find the inverse DFT of X(k) = {3,4,5,6}
Ans: The inverse DFT is defined as
N-1
x(n)=(1/N ) X x(k)ej2nnk/N n=0,1,2,3,...N-1
k=0
22. Explain various addressing modes of TMS processor.
Immediate.
Register Register indirect Indexed
& its detail explanation.
23 Derive the expression for steady state I/P Noise Variance and Steady state O/P Noise Variance
Write the derivation.
24. Explain briefly the periodogram method of power spectral estimation? Write the derivation with explanation.
25. Explain various arithmetic instruction of TMS processor.
All arithmetic instruction with explanation.
Design band pass filter with a frequency response Hd(e jw) =1 for -n/3<=iwi<=2n/3
0 otherwise
find the value of h(n) for N=11 find H(Z) plot magnitude response
Reg. No.: [
L
B.E./B.Tech. DEGREE EXAMINATION, APRIIVMAY 2008.
Fifth Semester (Regulation 2004)
Electronics and Communication Engineering EC 1302 DIGITAL SIGNAL PROCESSING (Common to B.E. (Part-Time) Fourth Semester Regulation 2005)
Answer ALL questions.
PART A (10 x 2 = 20 marks)
1. Define the properties of convolution.
2. Draw the basic butterfly diagram of radix - 2 FFT.
3. What are the merits and demerits of FIR filters?
4. What is the relationship between analog and digital frequency in impulse invariant transformation?
5. What are the three types of quantization error occurred in digital systems?
6. What is meant by limit cycle oscillations?
7. What is a periodogram?
8. Determine the frequency resolution of the Bartlett method of power spectrum estimates for a quality factor Q = 15. Assume that the length of the sample sequence is 1500.
9. What is meant by pipelining?
10. What is the principal feature of the Harvard architecture?
11. (a) (l) Discuss in detail the important properties of the Discrete Fourier
Transform. (8)
(ii) Find the 4 point DFT of the sequence (8)
x (n)~Cos tin!4.
Or
(b) (i) Using decimation-in-time draw the butterfly line diagram for 8 point FFT calculation and explain. (8)
(ii) Compute an 8 point DFT using DIF FFT radix 2 algorithm. (8) X(/i) = {l, 2, 3,4,4,3,2,11
12. (a) (i) Determine the magnitude response of an FIR filter (M = 11) and
show that the phase and group delays are constant (8)
M-l
=0
(ii) If the desired response of a low-pass filter is Hd(eiw)=e~jZw, -3jt/4 < uj < 3/4
0, 3/4 <|uj] < n (8)
Determine H (eiw) for M = 7 using a Hamming window.
Or
1
(b) (i) For the analog transfer function H (s) = (s + 2) c*etermne H (z) using impulse invariant technique. Assume T - Is. (6)
(ii) Design a digital Butterworth filter that satisfies the following
constraint using bilinear transformation (T =ls) (10)
0.9 <|tf(e,u'J<l for 0<w<x/2 |/f(f>J<0.2 for 2>nj 4<w < tz
13. (a) (i) Discuss in detail the Truncation error and Round-off error for sign magnitude and twos complement representation. (8)
(ii) Explain the quantization effects in converting analog signal into digital signal. (8)
(b) (i) A digital system is characterized by the difference equation y{n) = 0.9 (n-1) +%(.)
With jc(n) = 0 and initial condition y ( 1) = 12. Determine the dead band of the system. (4)
(ii) What is meant by the co-efficient quantization? Explain. (12)
14. (a) (i) Explain the Barlett method of averaging periodograms. (8)
(ii) What is the relationship between autocorrelation and power spectrum? Prove it. (8)
Or
{b> (i) Derive the mean and variance of the power spectral estimate of the Blackman and Tukey method. (8)
(ii) Obtain the expression for mean and variance of the auto correlation function of random signals. (8)
15. (a) (i) Describe the multiplier and accumulator unit in DSP processors. (6)
(ii) Explain the architecture of TMS 320 C5X DSP processor. (10)
Or
(b) (i) Discuss in detail the four phases of the pipeline techniques. (8)
(ii) Write short notes on :
(1) Parallel logic unit (4)
(2) Circular registers. (4)
3 V 4558
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