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National Institute of Technology 2005 B.Tech Electrical and Electronics Engineering Pulse and Digital Circuits - Question Paper

Monday, 04 February 2013 12:50Web

PULSE AND DIGITAL ELECTRONICS – FEB 2004
TUTORIAL SESSION two (9-2-2004 3:00 PM to 5:00 PM)

1) Transistors with Icmax = 200mA and Rbb’ = 50 ohms , Cc = six pF , CTe = five pF , B = 50 , fT = 10 Mhz Ts = 700ns are used to design a collector coupled astable multivibrator operating from 9V supply. (i) Design the system for 100kHz frequency and 50% duty ratio. Use a base overdrive factor of 5. The design should include the effect of transistor voltages. Use 0.5V, 0.7V and 0.2V for cut-in voltage, base-emitter voltage and saturation voltage respectively. The collector waveforms must have straight edges and the high level output should not go beneath eight Volt when a load resistance of 10k is connected at 1 of the output terminals. (ii) In the above design the base voltage of the off transistor is expected to begin at –8.3V.However it will be obtained to begin at a voltage lower in magnitude. This happens because the transistor which just now went OFF dumped its base stored charge through the timing capacitor into the collector of the companion transistor and in that process decreased the capacitor voltage almost instantaneously even before timing could begin. compute the stored base charge in the transistor and estimate the new voltage at which capacitor will begin timing. And also estimate the true running frequency. presume that the load resistance is not connected in solving this part. (iii) The load resistance of 10k is connected at 1 collector now. Will the Astable run at design frequency? Will the duty ratio be 50%? If not, compute the new values accounting for the saturation charge effect defined in (ii).

2) Design a Astable circuit to run from 12V supply using transistors with subsequent specs - Bmin = 100 , ICmax = 20mA Vebo = 9V.The output should be a square wave of duty ratio 20%.It should have straight edges and the frequency must be 50kHz. You will have to insert a diode in series with emitter line to avoid breakdown of BE junction when a transistor goes off. Account for the forward drop of the diode alongwith base-emitter drop in your design. What will happen if the diodes are not used ? Will the transistors get damaged ? If not , will the Astable continue on to function ? If yes, what will be the frequency of operation and duty ratio of operation ?

3) Design a Fixed Bias Transistor Bistable Circuit operating from +5V and –5V DC Supplies using transistors with Bmin = 50 and ICmax = 200mA. The high level output must be around 4.5V and the transistors must operate with a forward overdrive factor of five to 7. presume that the base saturation time constant is 500ns and compute the saturation charge storage charge in the Base. This charge flowing out through the commutating capacitor must not change its voltage by more than 10%. Design the commutating capacitor value suitably. With the computed value of commutating capacitance compute the settling time of the Binary. Use 0.5V, 0.7V and 0.2V for cut-in voltage, base-emitter voltage and saturation voltage respectively.

4) Design a Collector Coupled Monostable Circuit to operate from 12 Volt supply and to generate a 1ms pulse width. Show the trigger circuit design also. The pulse output should have an amplitude > 10 Volt. A load of 4.7k will be connected at the output and this has to be accounted for in the design. Specify all the components. State and justify your assumptions. Does it matter to which collector output the 4.7k load is connected? If it matters, then prepare 2 designs.

5) Design a collector coupled monostable circuit to produce a pulse of 10V amplitude and 10uS pulse width using a 12V supply voltage. The transistors have the identical specifications as in the Problem-1.Estimate the deviation in the pulse width due to the charge loss mechanism defined in Problem-1 in your design

6) obtain the transfer curve V0 Vs VI .(ii) obtain the maximum positive and negative voltages that can be applied at the input without causing saturation in any transistor.(iii) Plot the outputs Vo and V01 when Vi = five Sin 314t volts.(iv) Redesign the circuit to get Vut = 2.5V and Vlt = - 2.5V keeping the current in T3 at the identical value. Use the ? 10V supply. Plot the outputs Vo and V01 when Vi = five Sin 314t volts in this case too







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