Jawaharlal Nehru Technological University Kakinada 2010-2nd Sem M.Tech Electrical & Electronics Engineering Supplementary s DSP Processors & Architecture (ECE – VLSI System Design, VLSI&

Subject Code: B5502
M.Tech II Semester Supplementary exams June 2010
DSP Processors & Architecture
(ECE – VLSI System Design, VLSI&ES, ES and DECS)
Time: three Hours Max Marks: 60
ans any 5 ques. All ques. carry EQUAL marks
1. a) discuss with a block diagram a basic DSP system? elaborate the advantages and
disadvantages of programmable DSP processors?
b) A Signal consists of spectrum in the range 0-5 KHz which is to be sampled so that no aliasing
results. Determine the minimum sampling rate that can be used to sample the signal. If the sampling
rate must be eight KHz, determine the kind and the cutoff frequency of the anti-aliasing filter.
2. a) Prove that the dynamic range of a signal increases by 6dB for every additional bit used to
represent its value.
b) calculate the dynamic range and the percentage resolution for a block floating- point format with
a 4-bit exponent used in a 16-bit fixed point processor.
3. discuss the structure of:
(a) four × four Broun multiplier and
(b) Barrel shifter for 4-bits.
4. a) Distinguish ranging from maskable and non maskable, software and hardware interrupts.
b) discuss the concept of pipelining and how pipeline depth is measured? discuss different
stages in pipeline structure.
5. a) Draw the architecture of TMSC25 DSP and discuss every block clearly.
b) Write a 54XX program to calculate the formula y=ax1+bx2+cx3.
6. a) Write a program to implement FIR filters.
b) elaborate the architectural features of 54XX processor? discuss with a block diagram.
7. a) Draw the butterfly diagram for 2,4, and eight points using DITFFT.
b) Write a program to implement an 8-point DITFFT algorithm.
8. Write notes on:
(a) MCBSPS.
(b) DMA.

Earning:   Approval pending.