Jawaharlal Nehru Technological University Kakinada 2010-1st Sem M.Tech Computer Science SUBJECT CODE: C5803 REGULAR S COMPUTER ORGANIZATION AND ARCHITECTURE (CSE – Common to CSE and NN) - Q

1. (a) find the 10's complement of the subsequent six-digit decimal numbers:
i) 123900; ii) 090657; iii) 100000; and iv) 000000.
(b) Represent decimal number 8620 in (a) BCD; (b) excess-3 code; (c) 2421 code; (d) as a
binary number.

2. (a) Draw a binary counter with parallel load. Write the truth table.
(b) provide the function table of y to one line multiplexer.

3. Draw the block diagram of an associative memory. discuss match logic briefly.

4. define the architecture of 8086 CPU with a neat diagram.

5. define briefly the subsequent
(a) Address transfer instructions.
(b) Iteration control instructions.
(c) Interrupt instructions.

6. discuss the subsequent instructions with examples
(1) presume (2) DB (3) DT (4) ENDP (5) EXTRN (6) INCLLUDE.

7. Show the step-by-step multiplication process using Booth algorithm when the subsequent
binary numbers are multiplied. presume 5-bit registers that hold signed numbers. The
multiplied in both cases is + 15.
a. (+15) x (+13)
b. (+15) x (-13)

8. (a) discuss strobe control of asynchronous data transfer. What is its disadvantage? How does
handshaking method eliminate this problem?
(b) define programmed I/O with example.

Earning:   Approval pending.