Jawaharlal Nehru Technological University Kakinada 2010-2nd Sem M.Tech VLSI Design Supplementary s ALGORITHM FOR AUTOMATION (Common to VLSI, VLSI D, VLSI SD and VLSI & ES) - Question Paper

Subject Code: B5701
M.Tech II Semester Supplementary exams June 2010
ALGORITHM FOR VLSI DESIGN AUTOMATION
(Common to VLSI, VLSI D, VLSI SD and VLSI & ES)
Time: three Hours Max Marks: 60
ans any 5 ques. All ques. carry EQUAL marks
1. a) elaborate the most important entities in VLSI Design? discuss about
every of them?
b) Draw the sketch of Gajskis' Y-chart and discuss about the visualization of the three
design domains.
2. a) discuss briefly the general purpose methods for combinational optimization in VLSI
design.
b) Write short notes on Genetic Algorithms.
3. a) provide an algorithm for an exhaustive search by means of back tracking.
b) discuss the routing issues in floor planning methods of VLSI design.
4. What is meant by modeling and simulation? Differentiate grate level and switch level
modeling and simulation procedures with suitable example.
5. a) explain the basic problems and terminology employed in logic synthesis in VLSI
design.
b) discuss about ROBDD principles.
6. a) discuss about assignment and scheduling relevant to High-level Logic synthesis.
b) discuss about Iterative Data Flow.
7. a) provide the physical Design cycle for FPGAs and discuss about the identical.
b) discuss about partitioning for segmented models.
8. Write notes on any TWO:
(a) MCM technologies
(b) Chip Array based Approaches
(c) Multiple Stage Routing

Earning:   Approval pending.