Jawaharlal Nehru Technological University Kakinada 2008 B.Tech Electrical and Electronics Engineering PULSE AND DIGITAL CIRCUITS - Question Paper

Code No: 07A30401 Set No. 1
II B.Tech I Semester Regular Examinations, November 2008
PULSE AND DIGITAL CIRCUITS
( Common to Electrical & Electronic Engineering and Electronics &
Instrumentation Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
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1. (a) discuss the response of RC low pass circuit for exponestial input signal
(b) Derive the expression for percentage till for a square wave output of Rc high
pass circuit. [8+8]
2. (a) Design a diode clamper to restore a d.c level of +3 Volts to an input sinusoidal
signal of peak value 10Volts. presume drop across diode is 0.6 volts as shown
in the ?gure 2a.
Figure 2a
(b) Compare series diode clipper and shunt diode clipper. [8+8]
3. (a) discuss the phenomenon of latching in a transistor
(b) De?ne the subsequent for a transistor switch
i. Rise time
ii. Fall time
iii. Storage time
iv. Delay time. [8+8]
4. (a) discuss di?erent triggering methods of binary circuits.
(b) A collector coupled Fixed bias binary uses NPN transistors with hFE = 100.
The circuit parameters are VCC = 12v, VBB = -3v, RC = 1k O, R1 = 5k O,
and R2 = 10 k O. Verify that when 1 transistor is cut-o? the other is in
saturation. obtain the stable state currents and voltages for the circuit. presume
for transistors VCE(sat) = 0.3V and VBE(sat) = 0.7V. [8+8]
5. (a) In a current sweep circuit, discuss how linearity correction is made through
adjustment of driving waveform.
(b) Write the basic mechanism of transistor television sweep circuit. [16]
6. (a) What is the condition to be met for pulse synchronization?
1 of 2Code No: 07A30401 Set No. 1
(b) define synchronization with 2:1 frequency division with neat waveforms.
(c) De?ne the terms phase delay and phase jitter. [4+8+4]
7. (a) What is a sampling gate.
(b) Illustrate the principle of sampling gates with series and parallel switches and
compare them.
(c) Draw the circuit diagram of unidirectional diode gate and discuss its operation.
[16]
8. (a) Draw the circuit diagram of diode - resistor logic AND gate and discuss its
operation.
(b) Design a transistor inverter circuit (NOT gate) with the subsequent speci?ca-
tions. VCC = VBB = 10V, icsat = 10mA; hfemin = 30; the input is varying
ranging from 0 and 10V. presume typical junction voltages of npn silicon transistor.
[16]
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2 of 2Code No: 07A30401 Set No. 2
II B.Tech I Semester Regular Examinations, November 2008

Earning:   Approval pending.