Jawaharlal Nehru Technological University Kakinada 2008 B.Tech Electrical and Electronics Engineering SWITCHING THEORY AND LOGIC DESIGN - Question Paper

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3 of 3Code No: 07A3EC03 Set No. 3
II B.Tech I Semester Regular Examinations, November 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Instrumentation Engineering, Bio-Medical Engineering, Electronics &
Control Engineering, Electronics & Computer Engineering and
Instrumentation & Control Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
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1. (a) What is the necessity of binary codes in computers?
(b) Encode the decimal numbers 0 to nine by means of the subsequent weighted binary
codes.
i. eight four two 1
ii. two four two 1
iii. six four two -3
(c) Determine which of the above codes are self complementing and why?[2+12+2]
2. (a) List the Minterms and Maxterms for 3 binary variables. Draw the truth
table and express the Boolean function F(A,B,C) whose minterms are 1,3,5 ,7
as Canonica Sum of Minterms form.
(b) Simplify the subsequent Boolean functions to minimum number of literals:
i. F = X’Y’ + XYZ + X’Y
ii. F = X + Y[ Z + (X+Z)’ ]
(c) For the logic expression Y = AB’ + A’B:
i. find the truth table.
ii. Name the operation performed.
iii. Realize this using AND, OR, NOT gates. [8+4+4]
3. Simplify the subsequent Boolean expressions using K-map and implement them using
NOR gates:
(a) F (A, B, C, D) = AB’C’ + AC + A’CD’
(b) F (W, X, Y, Z) = W’X’Y’Z’ + WXY’Z’ + W’X’YZ + WXYZ. [16]
4. (a) Implement Full Adder using decoder and OR gates.
(b) Realize the Boolean function T(X,Y,Z) = S(1,3,4,5) using logic gates for haz-
ard free. [8+8]
5. (a) List the PLA programming table for the BCD to excess-3 code converter.
(b) A ROM chip of 4,096 × eight bits has 2 clip choose inputs and operates from
a 5-volt power supply. How many pins are needed for the integrated circuit
package? Draw the block diagram of this ROM. [8+8]
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6. (a) Draw the ckt diagram of four bit ring ring counter using D ?ip?ops and discuss
its operation with the help of bit trend.
(b) Distinguish b/w transition table and excitation table? [16]
7. discuss the subsequent related to sequential ckts with suitable examples.
(a) State diagram
(b) State table
(c) State assignment. [16]
8. (a) For the provided control state diagram find its equivalent ASM chart.
(b) Design control logic circuit as shown in ?gure 8b using multiplexers. [8+8]
Figure 8b
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2 of 2Code No: 07A3EC03 Set No. 4
II B.Tech I Semester Regular Examinations, November 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Instrumentation Engineering, Bio-Medical Engineering, Electronics &
Control Engineering, Electronics & Computer Engineering and
Instrumentation & Control Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
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1. (a) discuss the seven bit Hamming code.
(b) A receiver with even parity Hamming code is received the data as 1110110.
Determine the accurate code. [10+6]
2. (a) State and prove the subsequent Boolean laws:
i. Commutative
ii. Associative
iii. Distributive.
(b) obtain the complement of the subsequent Boolean functions and decrease them to
minimum number of literals:
i. (bc’+ a’d) (ab’ + cd’)
ii. b’d + a’bc’ + acd + a’bc
(c) Which gate can be used as parity checker? Why? [6+8+2]
3. (a) List the Boolean function simpli?cation rules in the K-map
(b) Simplify the subsequent Boolean function for minimal SOP form using K-map
and implement using NAND gates.
F(W,X,Y,Z) = S(1,3,7,11,15) + d(0,2,5) [4+12]
4. Design a combinational circuit that converts a decimal digit from 2,4,2,1 code to
8, 4,-2,-1 code. [16]
5. (a) The subsequent memory units are speci?ed by the no of words times the number
of bits per word. How many address lines and input-output data lines are
needed in every case?
i. 4K × 16
ii. 2G × 8
iii. 16M × 32
iv. 256K × 64.
(b) provide the number of bytes stored in the memories listed above. [16]
6. (a) Distinguish ranging from a state table and a ?ow table?
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(b) Draw the logic diagram and write functional table of an SR latch using NAND
gates. discuss the operation. [16]
7. For the provided minimal state - table:
(a) provide proper assignment.
(b) And design the circuit using D - Flip-?ops. [6+10]
current State Next state, out - put
X=0 X=1 X=0 X =1 (Z)
q1 q2 q1 0 0
q2 q3 q1 0 0
q3 q4 q5 0 0
q4 q4 q1 0 0
q5 q2 q1 one 0
8. (a) How do you indicate moore outputs and mealy outputs in an ASM block.
(b) find the ASM chart for the subsequent state transition.
begin for State T1; then if xy=00, go to T2 if xy=01, go to T3; if xy=10 go to
T1; otherwise go to T3. [8+8]
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Earning:   Approval pending.