Jawaharlal Nehru Technological University Kakinada 2008 B.Tech Electrical and Electronics Engineering SWITCHING THEORY AND LOGIC DESIGN - Question Paper

Control Engineering, Electronics & Computer Engineering and
Instrumentation & Control Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. (a) Why the binary number system is used in computer design?
(b) provided the binary numbers
a = 1010.1, b = 101.01, c =1001.1 perform the following:
i. a + c
ii. a - b
iii. a . c
iv. a / b.
(c) Convert (2AC5.D)16 to binary and then to octal. [2+10+4]
2. (a) Simplify the subsequent Boolean functions to minimum number of literals:
i. ( a + b )’ ( a’ + b’ )’
ii. y(wz’ + wz) + xy
(b) Prove that AND-OR network is equivalent to NAND-NAND network.
(c) State Duality theorem. List Boolean laws and their Duals. [4+4+8]
3. (a) elaborate don’t-care conditions? discuss its advantage with example.
(b) Simplify the subsequent Boolean function for minimal POS form using K-map
and implement using NOR gates.
F(W,X,Y,Z) = p(4,5,6,7,8,12) . d(1,2,3,9,11,14) [4+12]
4. (a) Design BCD to Gray code converter and realize using logic gates.
(b) Design 2*4 decoder using NAND gates. [10+6]
5. (a) Using PLA logic, implement a BCD to excess three code converter. Draw its truth
table and logic diagram.
(b) Disucss about kinds of sequential PCDs. [16]
6. (a) What do you mean by triggering. discuss the different triggering modes with
examples.
(b) Draw the logic diagram of a JK ?ip ?op and using excitation table, discuss
its operation. [16]
1 of 3Code No: 07A3EC03 Set No. 2
7. (a) Derive a circuit that realises the FSM de?ned by the state assigned table in
?gure beneath using JK ?ip ?ops.
current Next state Output
State w=0 w=1
y2y1 y2y1 y2 y1 Z
00 10 11 0
01 01 00 0
10 11 00 0
11 10 01 1
(b) obtain the state table for the subsequent state diagram as shown in ?gure 7b of a
simple sequential ckt. [8+8]
Figure 7b
8. (a) For the provided control state diagram, draw the equivalent ASM chart as shown
in ?gure 8a.
Figure 8a
2 of 3Code No: 07A3EC03 Set No. 2
(b) Design the control circuit using multiplexers for the above state diagram.[8+8]

Earning:   Approval pending.