Jawaharlal Nehru Technological University Kakinada 2007 B.Tech Electrical and Electronics Engineering PULSE AND DIGITAL CIRCUITS (3) - Question Paper

Code No: R059210202 Set No. 2
II B.Tech I Semester Regular Examinations, November 2007
PULSE AND DIGITAL CIRCUITS
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Electronics & Instrumentation Engineering
and Electronics & Telematics)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
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1. (a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T,
Where T is the period of an input ‘Em sin ?t'.
(b) What is the ratio of the rise time of the 3 parts in cascade to the rise
time of Single part of low pass RC circuit. [8+8]
2. (a) State and prove clamping -circuit theorem.
(b) A clamping circuit and input wave form is shown in figure 2b compute and
plot to scale the steady state output [8+8]
Figure 2b
3. Write Short notes on:
(a) Diode switching times
(b) Switching characteristics of transistors
(c) FET as a switch. [4+8+4]
4. (a) Consider the symmetrical emitter triggering circuit of the figure four with Rc=3Re,
R1=2R2, and VCC=6V. Indicate all the circuit voltages in the quiescent state
and indicate also the voltages immediately after a 5-V positive step is applied.
presume that D3 and D4 are always in the breakdown region and that either
D1 or D2 but not both in the breakdown region.
1 of 2
(b) Repeat part (a) for a 25-V step. What limits the maximum size of the input
step? What limits the minimum size of the input step? [16]
Figure 4
5. (a) Draw and clearly indicate the restoration time and flyback time on the typical
waveform of a time base voltage.
(b) Derive the relation ranging from the slope, transmission and displacement errors
(c) discuss how UJT is used for sweep circuit? [6+4+6]
6. (a) discuss the factors which influence the stability of a relaxation divider with
the help of a neat waveforms.
(b) A UJT sweep operates with Vv = 3V, Vp=16V and ?=0.5. A sinusoidal
synchronizing voltage of 2V peak is applied ranging from bases and the natural
frequency of the sweep is 1kHz, over what range of sync signal frequency will
the sweep remain in 1:1 synchronism with the sync signal? [8+8]
7. (a) What is sampling gate? discuss how it differ from Logic gates?
(b) What is pedestal? How it effects the output of a sampling gates?
(c) elaborate the drawbacks of 2 diode sampling gate? [6+6+4]
8. (a) Draw and discuss the circuit diagram of integrated positive RTL NOR gate
(b) Compare the RTL and DTL logic families in terms of Fan out, propagation
delay, power dissipated per gate and noise immunity. [8+8]
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Earning:   Approval pending.