Jawaharlal Nehru Technological University Kakinada 2007 B.Tech Computer Science and Engineering computer organisation - Question Paper

2. Design register selection circuit to choose 1 of the 4 4-bit registers content on
to bus. provide fuller explanation. [16]
3. (a) How do we decrease number of microinstructions. elaborate micro-subroutines?
[8]
(b) discuss nanoinstructions and nanometry. Why do we need them? [8]
4. (a) How many bits are needed to store the outcome addition, subtraction, multipli-
cation and division of 2 n-bit unsigned numbers. Prove. [8]
(b) What is overflow and underflow? What is the reason? If the computer is
considered as infinite system do we still have these issues. [8]
5. (a) What is the functioning of a Flash Memory? discuss. [8]
(b) provide the detailed picture of Memory Hierarchy. [8]
6. discuss the following:
(a) Asynchronous Serial Transfer
(b) Asynchronous Communication Interface. [8+8]
7. discuss 3 segment instruction pipeline. Show the timing diagram and show the
timing diagram with data conflict. [16]
8. (a) discuss the working of eight x eight Omega Switching network.
(b) discuss the functioning of Binary Tree network with two x two Switches. Show a
neat sketch. [8+8]
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Code No: R05310201 Set No. 3
III B.Tech I Semester Regular Examinations, November 2007
COMPUTER ORGANISATION
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Electronics & Instrumentation Engineering,
Electronics & Control Engineering and Electronics & Telematics)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. Distinguish ranging from fault detection and correction codes. What do you understand
by odd parity and even parity?. What is odd function and even function?. To
compute odd and even parity values which functions can be used? compute Odd
and even parity values for all hexadecimal digits 0-9 and A-F. [16]
2. (a) discuss about stack organization used in processors. What do you understand
by register stack and memory stack? [10]
(b) discuss how X=(A+B)/(A-B) is evaluated in a stack based computer. [6]
3. (a) How do you map micro-operation to a micro instruction address. [8]
(b) Hardwired control unit is faster than microprogammed control unit. Justify
this statement. [8]
4. (a) What is the use of fast multiplication circuits? Write about array multipliers.
[8]
(b) Multiply 10111 with 10011 using booths algorithm. [8]
5. (a) discuss how the Bit Cells are organized in a Memory Chip. [8]
(b) discuss the organization of a 1K x one Memory with a neat sketch. [8]
6. (a) What is Direct Memory Access? discuss the working of DMA.
(b) elaborate the various types of DMA transfers? discuss.
(c) elaborate the advantages of using DMA transfers? [8+4+4]
7. (a) What is pipeline? discuss. [8]
(b) discuss arithmetic pipeline. [8]
8. (a) discuss the working of eight x eight Omega Switching network.
(b) discuss the functioning of Binary Tree network with two x two Switches. Show a
neat sketch. [8+8]
? ? ? ? ?
1 of 1
Code No: R05310201 Set No. 4
III B.Tech I Semester Regular Examinations, November 2007
COMPUTER ORGANISATION
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Electronics & Instrumentation Engineering,
Electronics & Control Engineering and Electronics & Telematics)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. (a) discuss about different buses such as internal, external, backplane, I/O, system,
address, data, synchronous and asynchronous.
(b) discuss about daisy chain based bus arbitration. [16]
2. (a) Design a circuit transferring data from a 4bit register which uses D flip-flops
to a different register which employs RS flip-flops. [8]
(b) elaborate register transfer logic languages? discuss few RTL statement for
branching with their true functioning. [8]
3. (a) Support the statement Instruction Set Architecture has impact on the proces-
sors microarchitecture. [8]
(b) How do we decrease number of microinstructions? elaborate micro-subroutines?
[8]
4. (a) Draw a flow chart which explains multiplication of 2 signed magnitude fixed
point numbers. [8]
(b) Multiply 10111 with 10011 with the above procedure provided (a). Show all the
registers content for every step. [8]
5. elaborate the various kinds of Mapping Techniques used in the usage of Cache
Memory? discuss. [16]
6. (a) What is polling? discuss in detail.
(b) What is daisy chaining? discuss. [8+8]
7. (a) What is pipeline? discuss space-time diagram for Pipeline.
(b) discuss pipeline for floating point addition and subtraction. [8+8]
8. (a) elaborate the various physical forms available to establish an inter-connection
network? provide the summary of those. [6]
(b) discuss time-shared common bus Organization. [5]
(c) discuss system bus structure for multiprocessors. [5]
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Earning:   Approval pending.