Jawaharlal Nehru Technological University Kakinada 2007 B.Tech Computer Science and Engineering digital logic design - Question Paper

Code No: 07A3EC16 Set No.1
II B.Tech. I Semester Regular Examinations, November -2008
DIGITAL LOGIC DESIGN
( Common to Computer Science & Engineering,Information Technology and
Computer Science & Systems Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. (a) Convert the subsequent number with indicated bases to decimal [4×2=8]
i. (1 0 one 1 one 1)2 =
ii. (A three B)16 =
iii. (2 three 7)8 =
iv. (4 3)5 =
(b) find the 1’s and 2’s complements of the subsequent binary numbers [4×2=8]
i. one 1 one 0 one 0 one 0 =
ii. 0 one 1 one 1 one 1 0 =
iii. one 0 0 0 0 0 0 0 =
iv. 0 0 0 0 0 0 0 0 =
2. (a) Simplify the subsequent Boolean expression to a minimum number of literals.
i. F = (B C + A D) (A B + C D)
ii. F = WYZ + XY + X Z + YZ
(b) Express the subsequent function in sum of minterms and product of maxterms.
F(A, B, C, D) = B D + A D + BD [8+8]
3. Implement the subsequent Boolean function with NAND gates
F (x,y,z) = S (1,2,3,4,5,7). [16]
4. Design a code converter that converts BCD to excess - three code. [16]
5. (a) explain indetail about sequential circuit.
(b) Construct a JK ?ip-?op using a D ?ip-?op, a 2-to-1 multiplexer and inverter.
[8+8]
6. (a) Design a serial Adder in shift registers.
(b) Write a HDL behavioral description of shift register. [8+8]
7. (a) discuss about internal construction of four × four RAM
(b) Design a combinational circuit using a ROM. The circuit accepts a 3-bit num-
ber and generates an output binary number equal to the square of the input
number. [8+8]
8. discuss about SR Latch with example. [16]
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1 of 1Code No: 07A3EC16 Set No.2
II B.Tech. I Semester Regular Examinations, November -2008
DIGITAL LOGIC DESIGN
( Common to Computer Science & Engineering,Information Technology and
Computer Science & Systems Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. (a) Convert the subsequent numbers. [4×=8]
i. (53)10 = ( )2
ii. (231)4 = ( )10
iii. (1 one 0 one 1 0 1)2 = ( )8
iv. (4D.56)16 = ( )2
(b) Add and subtract in binary [4×=8]
i. one 1 one 1 and one 0 one 0
ii. one 1 0 one 1 0 and one 1 one 0 1
iii. one 0 0 one 0 0 and one 0 one 1 0
iv. one 1 0 one 0 0 one and one 1 0 one 1
2. (a) Implement the subsequent Boolean function using AND, OR and inverter gates.

Earning:   Approval pending.