Jawaharlal Nehru Technological University Kakinada 2007 B.Tech Chemical Science and Technology computer organisation - Question Paper

1. (a) discuss the terms compiler, linker, assembler, loader and define how a C
program or any other high level language program is executed in a system.
Indicate entire process with a figure.
(b) Distinguish ranging from high level and low level languages?. elaborate the re-
quirements for a good programming language? [16]
2. discuss about instruction, fetch, and decode cycles for a memory reference instruc-
tion. Draw a flow chart also to discuss the identical. Indicate clearly where and which
processor registers comes into picture. Now let us presume while a instruction is in
the middle of its decode cycle a interrupt is arrived. What is going to happen? Is
the instruction is completed or not. If we want to stop there itself and handle the
interrupt elaborate the difficulties? [16]
3. (a) What is a pipeline register. What is the use of it? discuss in detail. [8]
(b) Why do we need a few bits of current microinstruction to generate address of
the next microinstruction. Support with a live example. [8]
4. (a) Draw a flow chart which explains multiplication of 2 signed magnitude fixed
point numbers and provide an example for the working of the method. [8]
(b) discuss how we can identify arithmetic overflow is occurred while adding/subtracting
two signed numbers. Draw the circuit for performing addition/subtraction of
two four bit numbers that checks the over flow [8]
5. discuss the subsequent Cache Mapping Techniques
(a) Direct Mapping
(b) Set Associative Mapping. [8+8]
6. (a) What is daisy chaining? discuss with neat sketch.
(b) What is parallel priority interrupt method? discuss with neat sketch. [8+8]
7. Write short notes on the following:
(a) Risc pipeline
(b) Vector processing
(c) Array processors. [5+5+6]
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8. (a) discuss the working of eight x eight Omega Switching network.
(b) discuss the functioning of Binary Tree network with two x two Switches. Show a
neat sketch. [8+8]
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Code No: R059210505 Set No. 4
II B.Tech I Semester Regular Examinations, November 2007
COMPUTER ORGANIZATION
( Common to Computer Science & Engineering, info Technology
and Computer Science & Systems Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
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1. (a) provide means to identify on whether or not has overflow has occurred in 2s
complement addition or subtraction operations. Take 1 example for every
possible situation and discuss. presume four bit registers. Let If overflow register
E is also considered, check whether the outcome is corrector not [6]
(b) Represent -32.75 and 18.125 in single precision IEEE 754 representation. [10]
2. Design register selection circuit to choose 1 of the 4 4-bit registers content on
to bus. provide fuller explanation. [16]
3. (a) discuss nanoinstructions and nanometry. Why do we need them? [8]
(b) define advantages and disadvantages of horizontal and vertical microcoded
systems. [8]
4. (a) How many bits are needed to store the outcome addition, subtraction, multipli-
cation and division of 2 n-bit unsigned numbers. Prove. [8]
(b) What is overflow and underflow? What is the reason? If the computer is
considered as infinite system do we still have these issues. [8]
5. Compare and contrast Asynchronous DRAM and Synchronous DRAM. [16]
6. (a) What is polling? discuss in detail.
(b) What is daisy chaining? discuss. [8+8]
7. discuss the subsequent with related to the Instruction Pipeline
(a) Pipeline conflicts
(b) Data dependency
(c) Hardware interlocks
(d) Operand forwarding
(e) Delayed load
(f) Pre-fetch target instruction
(g) Branch target buffer
(h) Delayed branch. [8×2=16]
8. (a) What is the functioning of cross bar switch network? discuss. With a neat
sketch. [12]
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Code No: R059210505 Set No. 4
(b) How many switch points are there in a cross bar switch network that connect
’p’ Processors to ’m’ Memory modules. [4]
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Earning:   Approval pending.