Jawaharlal Nehru Technological University Kakinada 2009-1st Sem B.E Electronics

2. (a) Mention the DC noise margin levels of ECL 10K family.
(b) discuss the subsequent terms with reference to TTL gate.
i. Voltage levels for logic ‘1” & logic ‘0’
ii. DC Noise margin
iii. Low-state unit load
iv. High-state fan-out [6+10]
3. (a) discuss with an example the syntax and the function of the subsequent VHDL
statements.
i. Loop statement
ii. If, else and elseif statement
(b) Write a VHDL Entity and Architecture for a 3-bit ripple counter using Flip-
Flops. [8+8]
4. (a) Write a process based VHDL program for the prime-number detector of 4-bit
input and discuss the flow using logic circuit.
(b) discuss data-flow design elements of VHDL. [10+6]
5. Design a 16-bit ALU using 74×381 and 74×182 Ics. Implement VHDL source code
in data flow style for the identical. [16]
6. (a) Write a VHDL program for the circuit that counts number of Ones in a 16-bit
register using structural style of modeling.
(b) Design a 4×4 combinational multiplier and the write the necessary VHDL
program data flow model. [8+8]
7. (a) Design a 4-bit binary synchronous counter using 74×74. Write VHDL program
for this logic. Using data flow style.
(b) Design a modulo-60 counter using 74×163 Ics. [8+8]
8. (a) discuss how a 4×4 binary multiplier can be designed using 256×8 ROM.
(b) How many ROM bits are needed to build a 16-bit adder/subtractor with
mode control, carry input, carry output and two’s complement overflow out-
put? Show the block schematic with all inputs and outputs. [8+8]

Code No: S0401 / R05 Set No. 4
III B.Tech I Semester Supplimentary Examinations, May/June 2009
DIGITAL IC APPLICATIONS
( Electronics & Communication Engineering )
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks

1. (a) Design a CMOS transistor circuit that realizes the subsequent Boolean function.
f(x) = (a + b). (b + c)
Also discuss its functional operation.
(b) Design a 4-input CMOS AND-OR-INVERT gate. discuss the circuit with the
help of logic diagram and function table? [8+8]
2. (a) Design a transistor circuit of 2-input ECL NOR gate. discuss the operation
with the help of function table.
(b) A single pull-up resistor to +5V is used to give a constant-1 logic source
to 15 various 74LS00 inputs. What is the maximum value of this resistor?
How much high state DC noise margin can be given in this case? [8+8]
3. (a) Write a VHDL Entity and Architecture for the subsequent function?
F(x) = a + b + c
Also draw the relevant logic diagram.
(b) discuss the use of Packages provide the syntax and structure of a package in
VHDL [8+8]
4. (a) Write a process based VHDL program for the prime-number detector of 4-bit
input and discuss the flow using logic circuit.
(b) discuss data-flow design elements of VHDL. [10+6]
5. (a) Draw the logic symbol of 74×245 and discuss its operation?
(b) Write a VHDL program for 74×245? [16]
6. (a) Design a barrel shifter for 8-bit using 3 control inputs? Write a VHDL
program for the identical in data flow style.
(b) Write a behavioral VHDL program to compare 16-bit signed and unsigned
integers [8+8]
7. (a) Design an Excess-3 decimal counter using 74×163 and discuss the operation
with help of timing waveforms.
(b) It is necessary to generate six control lines in regular intervals sequentially.
Design the necessary circuit using 74×163 and 74×138. [8+8]
8. (a) With the help of timing waveforms, discuss learn and write operations of
SRAM.
(b) discuss the internal structure of 64K×1 DRAM. With the help of timing
waveforms explain DRAM access. [8+8]

Earning:   Approval pending.