Jawaharlal Nehru Technological University Kakinada 2009-1st Sem B.E Electronics & Communication Engineering III B.TechSupplimentary s, /e - Question Paper

Code No: S0401 / R05 Set No. 1
III B.Tech I Semester Supplimentary Examinations, May/June 2009
DIGITAL IC APPLICATIONS
(Electronics & Communication Engineering )
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. Draw the logic diagram equivalent to the internal structure of CMOS 4-input NAND
gate. Show the transistor circuit for this gate and discuss the operation with the
help of function table. [16]
2. (a) Draw the circuit diagram of basic TTL NAND gate and discuss the three
parts with the help of functional operation.
(b) discuss sinking current and sourcing current of TTL output. Which of the
above parameters decide the fan-out and how? [8+8]
3. (a) discuss with an example the syntax and the function of the subsequent VHDL
statements.
i. Process Statement
ii. Case Statement
(b) discuss Implicit and Explicit visibility of a Library in VHDL? [8+8]
4. Design a logic circuit to detect prime number of a 5-bit input. Write the structural
VHDL program for the identical. [ 16]
5. (a) Design a 32 to one multiplexer using 4 74×151 multiplexers and 74X139
decoder.
(b) Realize the subsequent expression using 74×151 IC [8+8]
f(Y ) = AB + BC + AC
6. A simple floating-point encoder converts 16-bit fixed-point data using 4 high
order bits beginning with MSB. Design the logic circuit and write VHDL data-flow
program. [16]
7. (a) Design an 8-bit universal parallel-in and serial out shift register with a control
input. Shift-left operation with control input one and shift-right operation with
control input 0 is to be performed.
(b) Design a serial binary adder Develop the VHDL program in data flow style
for simulating serial binary adder. [8+8]
8. (a) discuss the functional behavior of Static RAM cell Show the internal structure
of 8x4 static RAM and discuss.
(b) Design an 8×8 diode ROM using 74times138 for the subsequent data starting
from the 1st location. [8+8]
42, 2C,C4, FF,EA, 6D, 8F, 22

Code No: S0401 / R05 Set No. 2
III B.Tech I Semester Supplimentary Examinations, May/June 2009
DIGITAL IC APPLICATIONS
( Electronics & Communication Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks

1. (a) discuss how to estimate sinking current for low output and sourcing current
for high output of CMOS gate.
(b) Analyze the fall time of CMOS inverter output with RL = 100
, VL = 2.5V and CL =
10PF. presume VL as stable state voltage. [8+8]
2. (a) Design a TTL three-state NAND gate and discuss the operation with the help

Earning:   Approval pending.