Centre for Development of Advanced Computing(C-DAC) 2006 M.C.A -106 Computer System Architecture - Question Paper

End-Term exam
Second Semester [MCA] – MAY-JUNE 2006

Paper Code: MCA-106 Subject: Computer System Architecture
Time: three Hours Maximum Marks: 60

Q. one Attempt all parts :- (1 x 10 = 10)
(a) Name a computer machine that combines several instructions into a single
instruction.
(b) What is the memory addressing capability of a microprocessor which has 24
address pins?
(c) What is the advantage of having independent set of conditional codes?
(d) What is a monitor program?
(e) What is the head of a disk?
(f) Which industry is the primary user of MICR (Magnetic Inc Character
Recognition)?
(g) What prevents Risc pipeline to achieve maximum speed?
(h) Register A holds the 8-bit binary 11011001. Determine the B operand and the
logic micro-operation to be performed in order to change the value of A to
01101101?
(i) change (A+B)*C in reverse Polish notation?
(j) Determine the number of clocks cycles that it takes to process 200 tasks in a sigsegment
pipeline?

Q. 2
(a) What is difference ranging from instruction stream and data stream? (2)
(b) obtain out the avg. access time for a fixed head disk rotating at 300 rpm and
contains 10 sectors in a track? (3)
(c) What is the difference ranging from logical shift, circular shift and arithmetic shift.
provide suitable examples? (5)

Q. 3
(a) elaborate the differences ranging from external and internal interrupts? (3)
(b) describe the term Program Status Word. (2)
(c) Design a digital circuit that performs the 4 logic operations of exclusive-OR,
exclusive-NOR, NOR and NAND. Use 2 selection variables. Show the logic
diagram of 1 typical stage? (5)

Q. 4
(a) elaborate the differences ranging from Static Memory and Dynamic Memory? (2)
(b) elaborate 4 various kinds of pipelining? (2)
(c) Draw the flowchart for multiplying 2 floating point numbers? (6)
Q. 5
(a) How a subroutine call is various from branching? (2)
(b) Construct a 5-to-32 line decoder with 4 3-to-8-line decoders with enable and
one 2-to-4-line decoder? (8)

Q. 6
(a) If the program counter is always 1 count ahead of the memory location from
which the machine code is being fetched, how does the micro-processor change
the sequence of program execution with a jump instruction? (3)
(b) Formulate a mapping procedure that provides 8 consecutive micro instructions
for every routine. The operation code has 6 bits and the control memory has 2048
words? (3)
(c) Compare the Risc and Cisc architecture? (4)

Q. 7
(a) A 36-bit floating point binary number has 8 bits plus sign for the exponent and
26 bits plus sign for its mantissa. The mantissa is a normalized fraction. Numbers
in the mantissa and exponent are in signed magnitude representation. elaborate the
largest and smallest positive volumes that can be represented, excluding zero?
(4)
(b) discuss the difference ranging from hardwired control and micro-programmed control.
Is it possible to have a hardwired control associated with a control memory? (6)

Q. eight Write short notes on any two:- (5 x two = 10)
(a) RS 232 C protocol
(b) Associative Memory
(c) IBM PC bus.

Earning:   Approval pending.