Centre for Development of Advanced Computing%28C-DAC%29 2004 M.C.A -106 Computer System Architecture - Question Paper

End-Term exam
Second Semester [MCA] – MAY 2004

Paper Code: MCA-106 Subject: Computer System Architecture
Time: three Hours Maximum Marks: 60

Q. one A digital system has 16 registers, every with 32 bits. It is necessary to give
parallel data transfer from every register to every other register.
(a) How many lines are needed for transfer along four common bus? 3
(b) How many lines are needed for direct parallel transfer? 3
(c) If the registers from a scratch–pad memory, how is info transferred
from 1 register to other? Let the register in the memory be designated as R0 to
R15 6
List the sequence of micro operations for a transfer of contents of R6 to R13 .
Q. two (a) Construct a 5-to-32-line decoder with 4 3-to-8-line decoders with one
enable and 1 2-to-4-line decoder. 8
(c) find the 10’s complement of the subsequent 6 digit decimal number :
123900, 090 657, 100000, 000000. 4
Q. three (a) A sequential circuit has 2 D flip-flop A and B, 2 inputs X and Y and one
output Z. The flip-flop input equations and the circuit output are as follows :-
DA =XY + XA, DB =X1B + XA, Z=B
(i) Draw the logic diagram of the circuit.
(ii) Tabulate the state table. 8
(b) explain race around conditions in J-K flip-flop. 4
Q. four (a) describe the following:- 6
(i) Micro instruction
(ii) Micro Program
(iii) Control Memory
(b) Convert the subsequent numerical arithmetic expression into reverse Polish
notation and show the stack operation for evaluating the numerical outcome.
(3+4) [10(2+6) + 8] 6
Q. five (a) What is the difference ranging from Risc and Cisc processors? 6
(b) Draw the flowchart for multiplying 2 floating point-numbers. 6
Paper Code: MCA-106 Subject: Computer System Architecture
Note: Attempt any 5 ques..

Q. six discuss the subsequent :- 12
(a) Vector processor.
(b) Associative Memories

Q. seven discuss following: - 12
(a) Modes of data transfer
(b) Input/ output processor

Q. eight Write short notes on any 2 :- 12
(a) Cache memory
(b) Virtual memory
(c) Memory management hardware

Earning:   Approval pending.