# Centre for Development of Advanced Computing(C-DAC) 2003 M.C.A -106 Computer System Architecture - Question Paper

Saturday, 02 February 2013 01:35Web

End-Term exam

Second Semester [MCA] – MAY 2003

Paper Code: MCA-106 Subject: Computer System Architecture

**Time:**three Hours

**Maximum Marks**: 60

**Q.**one

**(**What is De-Multiplexer? How can you make decoder to function as a Demultiplexes?

**a)**Show this by a block diagram and truth tabl

**e.**5

**(**provided a 32 x eight ROM chip with an enable input, show the external connection

**b)**necessary to construct 128 x eight ROM with 4 chips and a decoder. 7

**Q.**two

**(**If we need to link 16 registers to a common bus, when every register is 32-bit

**a)**then, 6

**(**How many multiplexer will be required?

**i)****(**How many input lines are needed for every multiplexer? This should also

**i****i)**include adequate number of selection lines.

**(**Register A holds the 8-bit binary 11011001, determine the B operand and the

**b)**logic micro-operation to be performed in order to change the value in A to

**(**01101101

**i)****(**1111110

**i****i)****1.**6

**Q.**three

**(**With the help of flow chart, discuss the sequence of steps for an instruction

**a)**cycl

**e.**How does an interrupt change the sequence of events? 6

**(**provide the schematic diagram of a micro program sequence and briefly discuss

**b)**functions of its various components. 6

**Q.**four

**(**Convert the subsequent numerical arithmetic expressions into reverse polish

**a)**notation and show the stock operations for evaluating the outcomes. 6

(3+

**4)**[10 (2+

**6)**+ eight ]

**(**What do you understand by “Reduced instruction set computer” (Risc), How

**b)**are they differ from Cisc. 3

**(**What is difference ranging from direct addressing mode and indexed addressing

**c)**mode instruction. 3

**Q.**five

**(**explain the application of pipelines, illustrate through a system having 4

**a)**segment instruction pipelines. Also explain what is speed up in a pipeline

architectur

**e.**5

**(**compute the speed up in case of a computer with 4 floating-point pipeline

**b)**processors. every processor uses a cycle time of 40 µs. Total number of floating

point operation to be made is 400. 5

Paper Code: MCA-106 Subject: Computer System Architecture

Note: Attempt any 5 ques..

**(**Differentiate ranging from supercomputer & Multi-computers 2

**c)****Q.**six

**(**discuss Booth’s algorithm for multiplication. provide the schematic diagram of

**a)**the hardware needed to implement Booth’s algorithm. Depict the algorithm using

the hardware through a flow chart’s what happens when there is an overflow?

6

**(**A 48 bit computer stores floating point number is sign-magnitude form with

**b)**12 bits for exponent (including sign bit). obtain the range of numbers that can be

represented on this computer. 6

**Q.**seven

**(**What is I/O processor and elaborate its functions & advantages? Also explain

**a)**how I/O interrupts make more efficient use of CPU. 6

**(**In case of Direct-mapping cache & Fully associated Cache and considering

**b)**their merits explain / ans the following; 6

**(**rank these in terms of hardware complexity & implementation cost.

**i)****(**With every cache organization, what is the effect of block-mapping

**i****i)**policies on the hit-issue ratio.

**Q.**eight Write short note on any three:- three x 4

**(**Hardwired control and micro-program control

**a)****(**Virtual memory concept.

**b)****(**Overlapped Register windows

**c)****(**Arithmetic pipeline

**d)****(**SIMD array processor.

**e)**Earning: Approval pending. |