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Centre for Development of Advanced Computing(C-DAC) 2003 M.C.A -106 Computer System Architecture - Question Paper

Saturday, 02 February 2013 01:35Web

End-Term exam
Second Semester [MCA] – MAY 2003

Paper Code: MCA-106 Subject: Computer System Architecture
Time: three Hours Maximum Marks: 60

Q. one (a) What is De-Multiplexer? How can you make decoder to function as a Demultiplexes?
Show this by a block diagram and truth table. 5
(b) provided a 32 x eight ROM chip with an enable input, show the external connection
necessary to construct 128 x eight ROM with 4 chips and a decoder. 7

Q. two (a) If we need to link 16 registers to a common bus, when every register is 32-bit
then, 6
(i) How many multiplexer will be required?
(ii) How many input lines are needed for every multiplexer? This should also
include adequate number of selection lines.
(b) Register A holds the 8-bit binary 11011001, determine the B operand and the
logic micro-operation to be performed in order to change the value in A to
(i) 01101101 (ii) 11111101. 6

Q. three (a) With the help of flow chart, discuss the sequence of steps for an instruction
cycle. How does an interrupt change the sequence of events? 6
(b) provide the schematic diagram of a micro program sequence and briefly discuss
functions of its various components. 6

Q. four (a) Convert the subsequent numerical arithmetic expressions into reverse polish
notation and show the stock operations for evaluating the outcomes. 6
(3+4) [10 (2+6) + eight ]
(b) What do you understand by “Reduced instruction set computer” (Risc), How
are they differ from Cisc. 3
(c) What is difference ranging from direct addressing mode and indexed addressing
mode instruction. 3

Q. five (a) explain the application of pipelines, illustrate through a system having 4
segment instruction pipelines. Also explain what is speed up in a pipeline
architecture. 5
(b) compute the speed up in case of a computer with 4 floating-point pipeline
processors. every processor uses a cycle time of 40 µs. Total number of floating
point operation to be made is 400. 5
Paper Code: MCA-106 Subject: Computer System Architecture
Note: Attempt any 5 ques..
(c) Differentiate ranging from supercomputer & Multi-computers 2

Q. six (a) discuss Booth’s algorithm for multiplication. provide the schematic diagram of
the hardware needed to implement Booth’s algorithm. Depict the algorithm using
the hardware through a flow chart’s what happens when there is an overflow?
(b) A 48 bit computer stores floating point number is sign-magnitude form with
12 bits for exponent (including sign bit). obtain the range of numbers that can be
represented on this computer. 6

Q. seven (a) What is I/O processor and elaborate its functions & advantages? Also explain
how I/O interrupts make more efficient use of CPU. 6
(b) In case of Direct-mapping cache & Fully associated Cache and considering
their merits explain / ans the following; 6
(i) rank these in terms of hardware complexity & implementation cost.
(ii) With every cache organization, what is the effect of block-mapping
policies on the hit-issue ratio.

Q. eight Write short note on any three:- three x 4
(a) Hardwired control and micro-program control
(b) Virtual memory concept.
(c) Overlapped Register windows
(d) Arithmetic pipeline
(e) SIMD array processor.

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