Anna University of Technology Tirunelveli 2009 B.E Computer Science ,Advanced comptarchitecture. - Question Paper
Advanced compt. architecture. ques. paper is attached along with this. 601
B.E.VUlb Semester (Cmnjrt.Sckrtct) fcngg- Ertuniattoti ADVANCED COMPX ARCHITECTURE Pfcptr-CSE*4&l-C Time ellowed; 3 hours_Maximum Marks. 100
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Discuss the relative advantages of update and invalidate protocols fur bus fc&sed shared memo mulilprocessors. 10
Discuss the rclalive advantage of update and invalidate protocols for multi-node switched shared menwry muliiprocessors,
Discuss in brief
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(a) Multipic'issue machine
(b) Out of Older execution.
(a) When memory is implemented using DRAM organised as 2kx4t the failure of a single chip can result id ertor of up to low bits, ttevise an error correction scheme for device failure. Detail the scheme for m = 16. 10
(b) For a copybaclt cache (CBWA) and W = 0-5 using memory system - 200 nsh T4 = 100 ns+ n-af = 25T L s 16 compute Tamm , , T for
b*fjr
it) Unbuffered line transfers starting at tine addncss-
P.T.O,
(ii) Write buffer, line iransfers starting at line addrcss.
(iii> Buffer transfers wsih wrsprcound load, 1()
Discuss various wri te policies for caches. S
(a)
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<a)
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What do you mean by cache-mapping *? Explain the set associative mapping scheme for cache with the hfitp of a diagram, 2
Differentiate between static and d>rnwnic pipeJine. 6
Dt&cu*& the following:
7
7
(i) Branch elimination
(ii) Branch prediction stfatcgies.
Discuss ihc relative advantages and disadvantages of fiited and floating point representation of
& (a)
(1
7, (a)
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numbers.
Explain tte vimial io real address mapping. Give an example to support your answers, I**
Describe various phases in a processor design project.
Discuss the role of legistefi, evaluation stacks and data buffers in processor evaluation.
10
Write short nuics on i
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(a) Process Management
(b) D&ta Categories,
10
8,
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