Yashwantrao Chavan Maharashtra Open University 2006 Certification TES Digital Electronics - I - Question Paper

TES051/EE/20070811
Digital Electronics - I
Time : 180 minutes Marks : 100
Instructions for the students :
1. All ques. are compulsory.
2. “Long ans kind ques. (LAQ)” is a supply kind ques. of 20 marks,
which require typical ans of about 60-80 lines in about 32-40 minutes.
3. “Short ans kind ques. (SAQ)” is a supply kind ques. of five marks,
which require typical ans of about 15-20 lines in about 08-10 minutes.
4. Use of non-programmable kind of scientific calculator is allowed.
5. Draw neat diagrams wherever necessary.
6. presume suitable data if necessary.

Long ans kind ques. (LAQ’s)
1. (a) What is Octal Number System? discuss with an example
binary to octal and octal to binary conversion.
(b) Draw the logic symbol for every of the subsequent logic gates :
AND, OR, NOT, NOR, NAND.
Also write the Boolean expression and truth table for these
gates.


2. (a) Use De Morgan’s theorem to decrease the subsequent circuit :
(b) Develop a truth table for the original and equivalent circuit
used in part (a).
(c) Use Karnaugh map to decrease the expression :
Y = A + ABC + AB
(d) Use AND-OR-NOT gates to implement the subsequent :
Y = ABC + ABC + AB




3. (a) Draw an 8-bit even parity generator (seven data bits and
one parity bit) using 74LS280. Generate the parity bit for
0101010.
(b) What is a half adder? provide its truth table. Construct a half
adder using AND & NOR gates.


(c) i) obtain 2’s complement of 1011011.
ii) obtain 1’s complement of 1001001.
iii) Perform the subsequent subtraction using 2’s complement
subtraction: (1100011-1001001).
iv) Perform the subsequent subtraction using 1’s complement
subtraction : (1000101-1001000).

4. (a) What is surface mount technology?
(b) Draw a logic diagram of CMOS inverter and discuss its
working.
(c) define the different TTL subfamilies.


Short ans kind ques. (SAQ’s)

5. How will you troubleshoot logic gates ? 5
6. Using De Morgan’s theorem change the form of (A.B.C.) 5
7. What is a full addter ? Draw a diagram and its truth table. 5
8. Write a note on TTL Open-Collector gates. 5

Earning:   Approval pending.