West Bengal Institute of Technology (WBIT) 2008-7th Sem B.Tech Electronics and Communications Engineering Electronics & Comm ( - ) EDA for VLSI Design - Question Paper
CS/B.Tech05CE-NEW)/SEM-7/EC-7O2/O8/(O9) 3
ENGINEERING & MANAGEMENT EXAMINATIONS, DECEMBER - 2008
[ Full Marks : 70
Time : 3 Hours ]
GROUP - A ( Multiple Choice Type Questions)
Choose the correct alternatives for any ten of the following : 10 x 1 * 10
1.
1) Among the following which one has the greatest gate integration capacity ?
b)
d)
CPLD
ASIC.
a)
c)
FPGA
PLD
The fastest logic family is
a) TTL b) CMOS
c) ECL d) IIL.
The logic family which consumes least amount of power is a) DTL ' b) RCTL
c) CMOS d)
ii)
m
iv)
b)
d)
b)
d)
b)
v)
vi)
FPGA is a
a) full-custom ASIC c) programmable ASIC
Min-cut algorithm is a a) placement algorithm c) testing algorithm
VLSI design flow is a 0 cyclic process only
none of these.
semi-custom ASIC none of these. -
/
routing algorithm floor planning algorithm.
parallel process
c) sequential and cyclic process d)
none of these.
vll) VHDLisa
a) multi-threaded program b) a programming language like C
c) single user program d) sequential program.
viii) The suitable interconnect among the following is
a) Aluminium b) Gold
c) Copper d) Silver.
Minimum TTL gates required to design XOR gate is
ix)
b)
d)
a)
c)
Ten.
FPLD .
GPLD.
Ion implantation lithography.
x)
xl)
xil)
xiii)
" /
SPLD
FPGA.
xiv)
xv)
Layout
RTL Sfchematfc.
PLA and PAL are know as a) CPLD b)
c) SPLD d)
Bird's Beak phenomenon occurs in a) Diffusion b)
c) Oxidation d)
DRAM is widely used because
a) refreshing operation is not needed
b) of low cost and high density
c) of low power consumption
d) of high speed.
Scaling is done for
a) improving the switching speed
b) decreasing the power dissipation
c) reducing chip size
d) all of these.
LUT is used in ,
a) CPLD b)
c) ASIC d)
The output of physical design is a) Circuit b)
c) Logical model d)
Six
Twelve
' GROUP -B
( Short Answer Type Questions )
Answer any three of the following. 3x5= 15
2. a) What is Layout ? 1
b) Draw the Layout of CMOS Inverter. 2
c) What is FOX is IC fabrication ? 2
3. Implement a Full Adder in VHDL code using Mixed Style of Modelling. 5
4. a) What are |A-based and X-based designs in VLSI fabrication ? In which case full
capability of the Fab.Lab. can be utilised ? 2+1
b) For 0-5 Jim process what is the value of X ? According to the design rule, what will be the minimum widths of diffused region and metal interconnect lines ?
1 + 1
5. Draw the physical mask layout design for the following Boolean functions :
a) F = ( BA + DC) 4
5
2
1
2
b) F=[B + C)A.
6. a) What is cell Ubraiy ?
b) What is cell technology ?
c) What is Full custom design ?
GROUP-C (Long Answer Type Questions)
Answer any three of the following. 3 x 15 = 45
7. a) Write down the difference between CPLD and FPGA. 5
b) Write a program on 4-bit full adder using FA-1 bit. / 10
8. a) Explain the difference between Entity and architecture in a VHDL design. 4
b) What are the different styles of describing the Architecture in VHDL ? Explain each with an example. 3x3
c) Is mixed style description allowed in VHDL ? ' 2
9. a) Give a logic circuit example in which "Stuck-at-1" fault and "Stuck-at-O" fault are
?
}
indistinguishable. 5
b) Write down VHDL code for 4 to 1 mux and obtain the code for 16 to 1 mux using this 4 to 1 mux module. 10
10. a) Explain the n-well CMOS fabrication process with necessaiy diagram. 10
b) Draw the CMOS NAND gate and CMOS NOR gate using layout technique. 5
11. Write short notes on any three of the following : 3x5=15 0 Floor Planning
b) Application specific Integrated circuits
c) Test generation
d) Analog dfesign automation tools
e) Optimization of Combinational circuits.
' END
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| Earning: Approval pending. |
