University of Mumbai 2003 B.E Electronics & Tele-Communication Engineering ELEMENTS OF MICROELECTRONICS - Question Paper

ELEMENTS OF MICROELECTRONICS (DEC. 2003)
part I
1. Attempt any ten:
(a) What are the various kinds of metal semiconductor junctions ?
(b) What is the main purpose of the metallization ?
(c) When will be resistor formed in monolithic IC ?
(d) What is sheet resistance ?
(e) What is the use of SiO2 layer?
(f) What is the purpose of metallization process?
(g) what is the use of buried layer?
(h) What is the use of epitaxial growth in IC ?
(i) What is meant by parasitic capacitance in an IC ?
(j) To what voltage is the isolation island containing the resistors
connected ? Why ? (k) Can several transistors be placed in the identical isolation island ?
Explain. (1) What is the order of magnitude of the capacitance per square mil ?

2. (a) discuss how to estimate capacitance of wire due to fringing field.
(b) Give a list of nMOS fabrication masks.
(c) What are the advantages of twin tub process over n well process ?
(d) What is the minimum number if isolation regions needed to realize TTL NAND gate?
(e) What is the total needed to fabricate a 20kfi resistor whose width is one mil if R, = 200n / square.

3. Attempt any two:
(a) Consider an inverter circuit that has FET aspect ratios of (W/L)n = six and (W/L)p = eight in a process where k'n = 150µA/V3, VTn = +0.70V, k'p = 62nA/V2, VTp = -0.85V, VDD = 3.3V and Cout = 150fF. calculate rise and fall times.

(b) Calculate the threshold VT with no substance bias for NMOS silicon gate device that has NA = 1015/cm3 the thickness is 700A°. The positive ions per unit area at the Si-SiO2 interface is two x 1010/cm2, fF sub= 0.29V , ni = 1.4 x 1010/cm3 at 3000K, EOX= 3.5 x 10-13 F/c m, the relative permittivity of silicon is 11.8.

(c) The n-type epitaxial isolation region shown in fig is 10 mils long, five mils wide, and one mil thick and has resistivity of 0.2?-cm. The resistivity of the p-type substrate is 20?-cm. obtain the parasitic capacitance ranging from the isolation region and the substrate under
5V reverse bias. presume that the side walls contribute O.lpF/mil2.


4. Attempt any 1 : (a) Draw stick diagram and layout for two input CMOS NAND gate, (b) Draw stick diagram and layout for one bit CMOS shift register cell.


5. (a) discuss why scaling is done in MOS IC. provide in details partial scaling
and complete scaling. List merits and demerits of every kind.
(b) explain importance of ? based design rules for MOSIC.
part II
6. Attempt any one:
(a) Discuss the difficulties in processing a window mask which contains a wide variation of window sizes, i.e. both very large rectangles and minimum size square shapes. In particular, what issue would you other than when the process control is based on the monitoring of the smallest windows? How about the opposite case in which the process control is based on the largest window ?
(b) Design 3 masks for diffusion, window, and metal layers to realize a one K ?. resistor with n-type diffusion with sheet resistance of 100? per square and lead metal lines. The minimum features size allowed is one µm for line width and window opening. Also, 0.5mm extension of metal feature and diffusion feature over the window opening is needed.
7. (a) discuss double metal MOS process rules.
(b) An off chip capacitance load of pF is to be driven from CMOS inverters. Set out suitable arrangement giving improper channel L:W ratios and dimensions. compute the number of inverter stages needed and delay exhibited by the overall arrangement driving the 5pFload.
8. (a) NPN transistor is to be fabricated. define it's fabrication steps giving the mask sequence. Sketch the masking steps in the cross part view.
(b) Draw the neat diagram of the rector used for growing the single crystal epitaxial film on silicon
wafer. How will you do doping during the growth? define the factor affecting the quality of the
grown material.

9. (a) A CMOS inverter has to be fabricated. define it's fabrication Steps giving the mask sequence.
Sketch the masking steps in cross part view.
(b) discuss Ion implantation technique.

10. Attempt any one:
(a) Using the ? design rules, sketch a simple layout of an nMOS transistor on graph paper. Use a minimum feature size of three µn. Neglect the substrate connection. After you complete the layout, compute approximate values for Cg, Cab and Cdb. The subsequent parameters are provided. Substrate doping NA = 106cm-3, Drain/source doping ND = 1019cm-3, W = 15µm, L = 3µm and
tox= 0.05nm.

(b) The saturated enhancement load MOS inverter is shown in fig.
obtain i) VOH (assume Vin = 0.25V) and VOL.
ii) compute the W/l needed for M2 to achieve a VOL of 0.25V.

Earning:   Approval pending.