University of Mumbai 2004 B.E Electronics & Tele-Communication Engineering ELEMENTS OF MICROELECTRONICS) ( ) - Question Paper

ELEMENTS OF MICROELECTRONICS) (MAY 2004)
N. B.:
(1) ques. No. one is compulsory.
|2) ans any 4 out of remaining 6 ques..
(3) Assumptions made suitable clearry said.
(4) Assume suitable data wherever needed but justify the identical.
(5) Figures to the right indicate marks
(6) Illustrate answers with sketches wherever needed
(7) Answers to ques. Should be grouped and written together i.e. all answers to sub ques. of individual like ques. Nos. 1,2,3 etc. should answered 1 beneath the other.

(3) Use legible handwriting. Use a blue/black ink pen to write answers. Use of pencil should be done only to draw diagrams and graph.
part I
1. (a) Sketch to scale the cross part of a monolithic transistor fabricated on a 5-ml-thick silicon substrate. (3)

(b) Sketch the top view of a multiple emitter transistor. Show the isolation, collector, base and emitter regions (3)

(b) Explain how the parasitic channel, which couples unrelated NMOS transistors in an n-well process, is decreased. (4)
(c) Explain why substatdand well contacts on important in CMOS. (2)

(b) Explain why various criteria might be used to size transistor in lightly coupled small fanout. (4)
(I) How does a" dummy collector" current latchup ? (4)
2. (a) define the formation of resistor in integrated circuit. How will you optimize the design? |6)

(b) Draw the circuit diagram and stick diagram of two input CMOS NANDgate. |6)

(b) Incorporation of a burried layer in a bipolar device is a must for high frequency application. State why ? How are burried layer termed? (8)


3. (a) For the circuit showing in figure obtain (i) the minimum number (ii) the maximum number of isolation regions. Draw a monolithic layout of the circuit.
(b) define the importance of epitaxial film in integrated circuit fabrication. Draw the neat diagram of the rector y used for growing the single a crystal epitaxial film on three silicon water. How will you do the doping during the growth ? define the factors affecting the equality of the grown material.

4. (a) discuss what is partial scaling down and full scaling down MOS
circuit. provide merits demerits of such scaling operations. Does the
body effect of a process limit the number of transistors that can be
placed in series in a CMOS gate at low frequencies ? {10)
(b) A p well process has the subsequent layers: (10)
p-well active, h-plus, p-plus,poly, contact & metal. Draw the mask combinations for the subsequent : a p-transistor, an n-transistor , a Vss-contact, a VDD contact, a contact for un n-transistor source/drain, a single guard-ringed n-transistor & a double guard-ringed p-transistor.
5. (a) A MOS inverter has to be fabricated, define its fabrication steps
giving the mask sequence. Sketch the masking steps in cross-
sectional view (10)
(b) discuss metallization process of monolithic ZC. (10)
6. (a) discuss the subsequent terms-
i) Short channel effect. ii) Channel length modulation, iii) IC Crossovers. (12)
(b) A base diffusion layer length is 100 micrometer and its width is 10 micro meter. The sheet resistance of the layer is 1OOO ohm/square. compute its resistance. (4)
(c) A MOS Capacitor has an oxide thickness of 500A0. How much chip area is needed to find a capacitance of 200 PF ? presume Er for Si02 = 3.9. (4)
7.

(a) Explain dielectric isolation in detail. (10)
(b) A uniformly doped n-type silicon sulphate of 0.4 ohm-cm resistivity is subjected to a boron diffusion with constant surface concentration of four x lO17 cm-3. It is desired to form a PN junction at a depth of 2.5 microns. At what temperature should this diffusion be carried out if it is to be completed in one hour? (10)

Earning:   Approval pending.