Kurukshetra University 2010 B.Tech Electronics and Communications Engineering Vhdl assignment 1 & 11 - Question Paper

ECE DEPTT.

TUTORIAL SHEET 1

SUBJECT: VHDL

6^TH SEMESTER

 

Q1. DEFINE HARDWARE DESCRIPTION LANGUAGE AND ITS ADVANTAGES?

 

Q2. WHAT IS VHDL AND ITS FEATURES?

 

Q3. DEFINE ENTITY AND EXPLAIN DESIGN UNIT OF VHDL?

 

Q4. WRITE A VHDL PROGRAM FOR 2*4 DECODER USING STRUCTURAL

STYLE OF MODELLING?

 

Q5. WRITE A VHDL PROGRAM FOR HALF ADDER CIRCUIT USING DATA

FLOW MODELLING?

 

Q6. WRITE A VHDL PROGRAM FOR 1-BIT FULL ADDER USING MIXED STYLE

OF MODELLING?

 

Q7. DEFINE LIBRARY .EXPLAIN ONE EXAMPLE USING LIBRARY?

 

Q.8 DEFINE LIBRARY.EXPLAIN ONE EXAMPLE USING LIBRARY?

 

Q.9 DEFINE CONFRIGURATION DECLARATION WITH ONE EXAMPLE?

 

Q.10 DEFINE PACKAGE BODY WITH ONE EXAMPLE?

 

 

 

 

ECE DEPTT.

TUTORIAL SHEET 2

SUBJECT: VHDL

6^TH SEMESTER

 

 

 

Q.1 DEFINE ENTITY DECLARATION AND ARCHITECTURE BODY USING BEHAVIOUR MODELLING?

 

Q.2 EXPLAIN PROCESS STATEMENT WITH ONE EXAMPLE?

 

Q.3 DIFFERENCE BETWEEN SIGNAL AND VARIABLE?

 

Q.4 EXPLAIN VARIABLE AND SIGNAL ASSIGNMENT STATEMENTS ?

 

Q.5 WHAT IS INERTIAL AND AND TRANSPORT DELAYS ?

 

Q.6 EXPLAIN MODAL ANALYSIS OF VHDL?

 

Q.7 WRITE A VHDL PROGRAM USING WAIT ,IF STATEMENTS?

 

Q.8 DIFFERENCE BETWEEN STRUCTURE ,DATAFLOW BEHAVIOUR STYLE OF MODELLING?

 

Q.9 WHAT IS ASSERTION STATEMENTS.GIVE ONE EXAMPLE?

 

Q.10 WHAT IS SIMULATION. HOW IT IS PERFORMED