Kurukshetra University 2006 B.Tech Electronics and Communications Engineering VHDL & Digital Design- - Question Paper

 

Roll NO. ..............

BT-6/JX

VHDL & Digital Design

Paper: ECE-304(E)

Time: Three Hours] [Maximum Marks: 100]

 

NOTE: Attempt five questions in all, selecting at least one question from each unit.

 

UNIT-I

1. Explain CPLD in detail. 20

 

2. Explain in detail the compilation and simulation of VHDL

code using a suitable example. 20

UNIT-II

 

3.      Explain with suitable examples the concept of various DELAYS

in VHDL. 20

4.      Explain the concept of signal drivers and resolution function in

VHDL.Also write the resolution function for IEEE-1164standard

(9 valued logic) in tabular form.

 

UNIT-III

 

5. Write short notes on:

(a)          Function

 

(b)          Procedures. 20

 

6.                        Design a 1 bit full adder using K map. Write a code in VHDL for this adder using configuration specification. 20

 

 

UNIT-IV

 

7.                        Write short notes on :

(i)     Guarded Signal

(ii) Qualified Expression

(iii) Type conversion. 20

8. Write short note on Function attribute and Signal attribute. 20