Kurukshetra University 2009 B.Tech Electrical Engineering Digital Electronics( EE-204E) - Question Paper
4. Design a sequential circuit with two JK flip-flops A and B and two inputs E and x. If E = 0, the circuit remains in the same state regardless of the value of x. When E = 1 and x = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00, and repeats. When E = 1 and x = 0, the circuit goes through the state transitions from 00 to 11 to 10 to 01 back to 00, and repeats.
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5. (a) A flip-flops has a 5 ns delay from the time the clock edge occurs
to the time the output is complemented. What is the maximum delay in a 10-bit binary ripple counter that uses these flip-flops ? What is the maximum frequency the counter can operate reliably ?
(b) Design a counter with T flip-flops that goes through the following binary repeated sequence: 0,1,3,7, 6,4. Show that when binary states 010 and 101 are considered as don't care conditions, the counter may not operate properly. Find a way to correct the design.
6. (a) (i) Explain the differences between asynchronous and
synchronous sequential circuits.
(ii) Define fundamental-mode operation.
(iii) Explain the difference between stable and unstable states.
(iv) What is the difference between an internal state and a total state ?
(b) An asynchronous sequential circuit is described by the excitation and output functions :
Y = x,x2 + (x, + x2) y
z = y
(i) Draw the logic diagram of the circuit.
(ii) Derive the transition table and output map.
(iii) Obtain a two-state flow table.
(iv) Describe in words the behavior of the circuit.
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7. (a) Using the actual output transistors of two open-collecter TTL
gates, show (by means of a truth table) that when connected together to an external resistor and Vcc, the wired connection produces an AND function.
(b) Prove that two open-collector TTL inverters, when connected together, produce the NOR function.
8. (a) Determine the high-level output voltage of the RTL gate for a
fan-out of 5.
(b) Determine the minimum input voltage required to drive an RTL transistor to saturation when h_ = 20.
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(c) From the results in (a) and (b), determine the noise margin of the RTL gate when the input is high and the fan-out is 5.
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700
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| Earning: Approval pending. |
