SRM University 2007 B.Tech Electronics and Communications Engineering BANK of Introduction to VLSI Design - Question Paper

4. What is logic expander and shared expander. explain any four significant differences ranging from logic expander and shared expander and their role in FPGA architecture.
5. Explain in detail about the different kinds of ROM available in FPGA design methodologies with a neat sketch.
6. Explain in detail about different combinational PLD’s available with neat sketch.
7. Implement the subsequent Boolean function using suitable PAL and PLA.
i. F (a, b, c, d) = ?m(0,2,3,5,7,9,15) ii) F (a, b, c) = AB| + AC + A| BC|
8. Explain in detail about the different kinds of sequential PLD’s available with a neat diagram and their respective advantages and disadvantages.
9. Explain in detail with a neat sketch about the different Full Custom IC current in ASIC design methodologies.
10. Explain in detail with a neat sketch about the different Semi Custom IC current in ASIC design methodologies.
11. Explain what is Masked Gate array implementation. discuss the different kinds of MGA with a neat sketch.
12. Explain what is structured gate array architecture with a neat sketch.
13. (a) explain any five significant difference ranging from Full custom IC & Semi custom IC design.
(b) explain any five significant differences ranging from Masked Gate Array (MGA) and structured gate array architecture.
Unit – IV
PART – A
1. Give the switching power dissipation of the CMOS inverter?
2. What do you mean by noise margin and how to equalize asymmetry in noise margin?
3. Give the 2 main points of difference ranging from expectations and realization which characterize many of the design beginners?
4. Determine the propagation delay through cascaded pass transistors?
5. Explain the factors influencing option of layer for wiring?
6. Explain the restrictions associated with MOS pass transistor and transmission gates?
7. Name a few of the key design parameters that is concerned by the designer?
8. Explain hand crafted design?
9. What do you mean by CIF and also state its purpose?
10. Explain the items that should be in designer’s tool box?
11. Explain circuit description languages?
12. Explain behavioral verification and physical verification?
13. Give the different kinds of simulators?
14. Explain how to improve transistor modeling?
15. Differentiate circuit simulators and timing simulators?
16. Give the 3 factors that conspire to create considerable difficulties for the test engineer?
17. Define test coverage and also explain the classification of faults?
18. Give a set of physical fault models?
19. Give the 3 main ways to facilitate test processes?
20. Discuss the disadvantages of asynchronous sequential logic?

PART – B
1. Explain the scan path design technique using suitable example and also define Level-sensitive scan design (LSSD)
2. Explain the subsequent a) BIST – signature analysis
b) BIST – LFSR c) BIST – BILBO
3. Explain testing of combinational logic using suitable example?
4. Explain testing of sequential logic using suitable example?
5. Write a note on a) Design rule checkers (DRC)
b) Circuit extractors c) Simulators
6. Explain in detail the ground rules for successful design?
Unit – V
PART- A
1. What are the important features of VHDL?
2. Differentiate a signal and variable?
3. What are the various kinds of modeling in VHDL?
4. Explain ‘case’ statement in VHDL with an Example.
5. Explain ‘BLOCK’ statement in VHDL with an Example.
6. Explain ‘Process’ statement in VHDL with an Example.
7. Explain ‘Generate’ statement in VHDL with an Example.
8. What is Test Bench?
9. Compare VHDL and Verilog in 2 aspects.
10. Give the behavioral model for JK flipflop.
11. Give the behavioral model for D & T flipflop.
12. Give the data flow model for half adder and half subtractor.
13. Give the dataflow model for full adder.
14. Give the dataflow model for full subtractor.
15. Write short notes on delays in VHDL.
16. What is component instantiation?
17. Differentiate sequential from concurrent signal assignment statements.
18. Write short notes on “Wait” statement.
Part – B
1. Explain the different modeling methods used in VHDL with an example.
2. Explain in detail about the principal of operation of VHDL Simulator.
3. Write the VHDL program for four bit counter.
4. Write the VHDL program for full adder in all 3 kinds of modeling?
5. Write VHDL program for 4:1 MUX and 1:4 DEMUX using behavioral modeling.
6. Write VHDL program for encoder and decoder using structural modeling.
7. With an example discuss in detail the test bench creation.
8. Write a verilog program for
1) Full Adder 2) Shift Register.

Earning:   Approval pending.