SRM University 2007 B.Tech Electronics and Communications Engineering BANK of Introduction to VLSI Design - Question Paper

14. Realize the formula Y= (AB+CD)' in
a) NMOS technology b) CMOS technology
15. Draw the circuit diagram, stick diagram of NMOS Exclusive-OR gate.
16. Realize the subsequent equations using CMOS,NMOS,and PMOS transistors?
a) Z= ((A.B.C) +D)'. b) Z= (((A.B) +C).D)'.
c) Z= ((A.B) +C(A+B))'. d) Z= A.B'.C'+A'.B'.C+A'.B.C'+ A.B.C.
17. Realize the subsequent using CMOS: Z(A,B,C,D) = ?(3,7,13,15) + D(11,12,14).
18. Discuss in detail the scaling factors for device parameters and show the effects of scaling for constant field model.
19. Discuss in detail the scaling factors for device parameters and show the effects of scaling for constant voltage model.
20. Discuss in detail the scaling factors for device parameters and show the effects of scaling for combined voltage and dimension scaling model?

Unit – III
PART – A
1. State the different kinds of ROM available. Differentiate ranging from masked ROM & PROM.
2. State the different kinds of PLD’s available. Differentiate ranging from PAL & PAL.
3. Differentiate ranging from CPLD & FPGA.
4. Explain what is macro cell with an example.
5. Differentiate ranging from semi custom IC design and Full custom IC design.
6. Differentiate ranging from Standard cell based ASIC and Gate array based ASIC design methods.
7. Explain with a neat sketch about programmable ASIC.
8. Differentiate ranging from programmable logic device and FPGA.
9. Explain elaborate Mega cells.
10. State any three significant advantages of Standard cell based ASIC.
11. Differentiate ranging from channeled gate array and Channelless gate array.
12. State the advantages of FPGA logic design.
13. Explain what is Logic expander.
14. Implement the subsequent Boolean function using suitable ROM.
F( a, b, c, d ) = ?m ( 0, 2, 5, 7, 9, 12, 15 )
15. Implement the subsequent Boolean function using suitable PLA.
F1 = AB| + AC + A| BC| F2 = ( AC+BC )|
16. What is Field Programmable Logic Sequencer (FPLS)?
17. What is Masked gate array?
18. State any three important advantages of Full Custom IC design.
19. Mention any three important features of Standard cell based IC design.
PART – B
1. Explain with a neat sketch the architecture of CLB’s available in Xilinx XC 3000 series FPGA.
2. Explain with a neat sketch the architecture of an ALTERA FLEX FPGA device.
3. Explain with a neat diagram the architecture of the base cells current in ALTERA MAX FPGA device.

Earning:   Approval pending.