SRM University 2007 B.Tech Information Technology IT100 -DIGITAL ELECTRONICS - Question Paper

9) Define Read-only memories?
10) Draw the diagram and truth table for a 2-to-4 line decoder?
11) List out the advantages of ROM?
12) Draw the diagram of a ROM which has three input lines and four output lines?
13) State the realization of multiple-output network using a decoder?
14) Draw the basic ROM structure?
15) List the basic kinds of ROMs?
16) State the ROM realization of code converter?
17) State the features of EPROM’s?
18) List out the advantages of EPROM over PROM?
19) What is a programmable logic device?
20) Define PLA?
21) Draw the programmable logic Array structures?
22) Draw the PLA with three input and four outputs?
23) Define PALs?
24) Draw the PAL structure?
25) Draw the block diagram of Binary to ASCII converter?
26) Define a demultiplexer?
27) List the different steps involved in the design of code conversion networks?
28) What is a multi-level network?
29) Draw the block diagram of an encoder
30) List the characteristic of an encoder?
31) Define parity?
32) List the different techniques involved in parity generator?
33) List the characteristic of a parity checker?
34) Define memory devices?
35) List the different categories of memory devices?
36) List the different steps involved in the design of two-level multiple –o/p networks?
37) List the different kinds of PLD?
38) Distinguish ranging from the ROM implementation and PAL implementation of Boolean functions?



PART-B

1) Elaborately discuss the design of a two-level multiple o/p networks?
2) Design a code conversion network of BCD to excess three code?
3) Design a code conversion network of BCD to gray code?
4) Design a code conversion network of gray code to BCD?
5) Design a code conversion network of BCD to ASCII code?
6) Design a 4-to-10 line decoder?
7) Design a structure of a 8-Word X4-bit ROM?
8) Design the structure of PLA with three inputs and four outputs?
9) Find a 2 –level multiple o/p AND-OR gate network to realize the subsequent functions. Minimize the needed no of gates (6 gates minimum)
F1=a1c+a1d1+b1c and F2=c1d1+ab1+ac1
F1=ac+ad+b1d and F2=a1b1+a1d1+cd1

10) Design a network of AND and OR gates to convert from excess -3 code to 8421 BCD code?
11) Draw the logic diagram of BCD to decimal decoder and discuss its working in detail?
12) Design 1:8 demultiplexer using 2 1:4 demultiplexer
13) Explain elaborately parity generator and checker for even and odd parity
14) Design a decimal to BCD encoder?

Earning:   Approval pending.