SRM University 2007 B.Tech Electronics and Communications Engineering Bank :: Digital Systems - Question Paper

7. Give the logical expression for sum and carry for a half-adder.
8. What are the applications of multiplexers?
9. What is a code converter?
10. How does a multiplexer differs from an Encoder?
11. What is an Encoder?
12. What is the minimum number of selection lines needed for selecting 1 out of ‘n’ input lines?
13. Implement two input NAND gate function y = (ab)’ using a 2:1 MUX.
14. Distinguish ranging from a decoder and a demultiplexer.
15. What is a Magnitude comparator.

Part – B
1. How will you build a 16 input MUX using only four input multiplexers.
2. Design and implement a Full adder.
3. i) Draw the circuit of half-adder using only NAND Gates.
ii) Design a 4-bit Magnitude comparator.
4. Design and implement a full subtractor.
5. Design a gray to BCD code converter using logic gates.
6. What is an 8421 adder? elaborate the rules for 8421 addition? define the working of and 8421 adder by suitable diagram.
7. Design converter that converts four bit binary info to gray info.
8. A four bit binary is represented as A3 A2 A1 A0 with A0 equal to the LSB. Design a logic circuit that will produce a HIGH output whenever the binary number is greater than [0010] and less than [1000].

9. Design and implement a circuit that converts BCD to Excess – three Code.
10. Implement the subsequent Boolean function using Suitable MUX
i) F(a,b,c) = ?m(1,4,5,6,7)
ii) F(a,b,c,d) = ?m(1,4,5,6,7,10,11,13,15)
11. Implement the subsequent Boolean function using Suitable Decoder
i) F(a,b,c) = ?m(1,4,5,6,7)
ii) F(a,b,c,d) = ?m(1,3,5,7,10,11,13,15)
12. Implement a Octal to binary code conversion using suitable combinational logic circuit.
13. Design a 4-bit priority Encoder.
14. Design and implement a combinational circuit that converts binary to BCD.





UNIT – IV
Part – A

1. Realize T-flip flop using JK flip-flop?
2. Explain sequential circuit with an neat sketch?
3. Define a Flip-Flop with a suitable sketch?
4. Draw the Basic flip-flop circuit.
5. Give the excitation table for JK flip-flop?
6. Explain the race around condition?
7. What is the state diagram?
8. Distinguish ranging from combinational & sequential logic?
9. Give the characteristic table for JK flip-flop
10. Realise D Flip-flop using JK flip flop.
11. Realize the JK flip-flop using NAND gate only?
12. What is the excitation table for D flip-flop?
13. What are the advantages & disadvantages of synchronous over asynchronous counter?

14. How many flip-flop will be complemented in a 10-bit binary ripple counter to reach the next count after the subsequent count i)1001100111; ii)0011111111; iii)1111111111

15. Define edge triggering with a suitable example?
16. What is meant by a counter?
17. What is meant Universal shift register?
18. Mention the application of shift register.
19. Write the characteristic formula for a) JK Flip-flop b) T flip-flop c) D flip-flop
20. write the excitation table for a) T flip-flop b) SR flip-flop
21. Distinguish ranging from Mealy and Moore’s state machine with an example?




Part – B
1. Design a counter with subsequent repeated binary sequence 0,4,2,8, 1,6, nine ….. using a) JK flip-flop b) D flip flop.

2. With relevant diagrams and truth table discuss the operation four bit ripple counter.
3. Design a decade counter.
4. Design a counter using T flip-flop to count sequence 0,1,2,3,4,0,1,2…..
5. Design a 4-bit binary synchronous counter with a D Flip-flop
6. Design a 8-bit ring-counter with a suitable flip-flop.
7. Design a 4-bit switch-tail ring counter / Johnson counter with a suitable flip-flop.
8. Design a 4-bit Universal Shift Register
9. Design a subsequent input sequence 01010110100 using the suitable logic.
10. Design a 4-bit Binary Up-Down Counter
11. Design a 4-bit BCD ripple counter with relevant diagram.
12. Draw the logic diagram of a 4-bit register with four D-Flip flops and 4 four x1 MUX’s with mode selection inputs s0, s1. The register operation according to subsequent func.
s1 s0 Reg. Operation
---------------------------------------------
0 0 No change
0 1 Complements the 4 outputs
one 0 Clear register to 0
1 1 Load parallel data

Unit – V
Part – A
1. How many address lines will be there in 2k X eight organized RAM chip?
2. Compare static RAM with Dynamic RAM.
3. Distinguish ranging from EPROM and EEPROM.
4. What does burning a ROM mean?
5. What is a PLD?
6. What are the major draw backs of EEPROM?
7. How many data inputs, data outputs and address inputs are needed for 1024 X four ROM?

8. Construct 32 X four ROM using five to 32 line decoders. discuss its operation.
9. What is dynamic RAM?
10. Distinguish ranging from PLA and PAL.
11. How many address lines and input-output data lines are needed for the subsequent
a) 2G X eight b) 16M X 32 c) 256K X 64
12. How many 32K X eight RAM chips are needed to give a memory capacity of
256KB
13. Construct a 128 X eight ROM using a 32 X eight ROM chip with enable input & decoder

Part – B
1. Distinguish ranging from EPROM and EEPROM with suitable example.
2. Draw the logic diagram of a 64 bit ROM and discuss it.
3. Draw the 2 dimensional addressing of RAM with block schematic.
4. List out the applications of the PAL.
5. A RAM chip has a capacity of 1024 words of eight bits each(1k X 8)
a) How many address lines and data lines needed in the chip?
b) How many chips are needed to construct a 16 X 16 RAM?
c) How many address and data lines are there in 16k X 16 RAM?
6. List out the applications of ROM.
7. Implement the subsequent function using suitable ROM
A(x,y,z) = ? (1,2,4,6)
B(x,y,z) = ? (0,1,6,7)
C(x,y,z) = ? (2,6)
D(x,y,z) = ? (1,2,3,5,7)

8.Tabulate the PLA programming table for the 4 Boolean functions listed beneath
A(x,y,z) = ? (1,2,4,6)
B(x,y,z) = ? (0,1,6,7)
C(x,y,z) = ? (2,6)
D(x,y,z) = ? (1,2,3,5,7)
Minimize the number of product terms.

8. Design a BCD-to-Excess-3 code converter with a suitable PLA logic











ques. BANK
EC201 – DIGITAL SYSTEMS

Earning:   Approval pending.